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Selecting Test Features
Stressing Optical Clock Recovery Circuits
Stressing Optical Clock Recovery Circuits
Description
This test is essentially designed for testing optical clock recovery circuits in the
presence of long runs of zero's or one's (after scrambling). The test function page
allows control of the test pattern and the block length. The maximum block length is
2 bytes less than the width of the Virtual Container.
When the test is enabled, the instrument applies the selected pattern immediately
after the first row of Section Overhead bytes after scrambling. The location of the
start of the pattern is byte 4 at 52 Mb/s (i.e. after the first three bytes of overhead),
byte 10 at 155 Mb/s, byte 37 at 622 Mb/s and byte 145 at 2488 Mb/s. The remainder
of the Virtual Container will contain the signal structure and pattern as defined on
the TRANSMITTER, MAIN SETTINGS page.
The payload is overwritten in such a way that the transmitted B1 and B2 values are
correct.
When using this feature to test network equipment clock recovery, long runs of
zero's may be inserted at the input of the UUT (unit under test) and by monitoring
B1 and B2 at the UUT output, error free transmission can be verified.
The stress test is available at all optical rates.
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