Fully Exercising Pos Hardware Architecture - Agilent Technologies OmniBER 718 SDH User Manual

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Packet over SDH (POS)

Fully Exercising POS Hardware Architecture

Fully Exercising POS Hardware Architecture
Description
POS hardware operating at high speeds uses wide bus architectures (that is, internal
buses which are several bytes wide). To ensure correct operation the hardware needs
to be fully exercised (stressed) so that all 'corner cases' are caught. This is done by
generating traffic with varying packet and gap sizes, sending the smallest packets at
highest speed, longest packets, scrambling and exercise of the octet stuffing and
destuffing. It may also include sending packet sizes rarely encountered in live
networks (such as packet sizes which are not rounded to 4-byte boundaries).
With the OmniBER 718 you generate traffic profiles to successfully exercise POS
hardware using the methods described. The following figure illustrates the traffic
profiles offered in the OmniBER 718.
Fixed packet size and gap
If you select a fixed packet and gap you can check different phases of the wide-bus
architecture. For example selecting gap sizes of 1, 2, 3 and 4 will test all 4 byte
phases of a 4-byte architecture.
Random packet size
With random packet sizes, the maximum and minimum size can be set.
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