External Signals; Dreq[1:0]; Dack[1:0]; Memory Map/Register Definitions - Freescale Semiconductor MCF5480 Reference Manual

24.2

External Signals

24.2.1

DREQ[1:0]

These active-low inputs provide external requests from peripherals needing DMA service. When asserted,
the device is requesting service. Depending on the operating mode, either the level of the signal is sampled
at the rising edge of the system clock or an edge detect is used to recognize a high to low change. These
inputs have no effect when the task enable control bit is cleared.
24.2.2

DACK[1:0]

These active-low outputs indicate when the DMA request is being acknowledged. These outputs can be
programmed to assert from one to four system clocks, depending on the operating mode. The DACK
signals are programmed to recognize the address on one of the DMA address buses and assert if a match
is made. The size of the address space can be increased by setting the EREQMASKn address mask bits.
See Section 24.3.4.3, "External Request Address Mask Register (EREQMASK),"
24.3

Memory Map/Register Definitions

Memory organization is described in the register array pointed to by the memory base address register
(MBAR). Information necessary to enable the DMA is described in this register array at the predetermined
offset of MBAR + 0x8000.
The TaskBAR identifies a location for the table of pointers to multichannel DMA tasks. Each task has an
entry that contains information about the microcode's location in memory as well as a pointer to the
variable table to be used in the task.
In the MCF548x, DMA memory is controlled both by the programmer and by the DMA engine itself.
24.3.1

DMA Task Memory

The DMA uses memory provided by the user to store task code and structures.
of the structures in DMA memory. This memory region may exist in any addressable storage, such as
system SRAM or external memory.

24.3.1.1 Task Table

The task table is a memory region containing pointers to each MDE task. A task table base address register
(taskBAR) sets the location of the task table itself. Each entry in the task table contains pointers to the
task's first descriptor, last descriptor, variable table, and other task-specific information. The task table
must be aligned to a 512-byte boundary.

24.3.1.2 Task Descriptor Table

Each task descriptor table is a memory region containing the descriptors that comprise the task. Each task
descriptor table is composed of Data Routing Descriptors (DRD) and Loop Control Descriptors (LCD).
The pointers in the task table define the beginning and end of each task descriptor table; see
Task descriptor tables must be aligned to a longword (32 bit) boundary.
Freescale Semiconductor
MCF548x Reference Manual, Rev. 3
External Signals
for more information.
Figure 24-2 shows some
Figure 24-2.
24-3