Global Status/Control Register (Pcigscr) - Freescale Semiconductor MCF5480 Reference Manual

registers are accessed primarily internally as offsets of MBAR, but can also be accessed by an external PCI
master if PCI base and target base address registers are configured to access the space. See
"Address Maps," on configuring address windows.

19.3.2.1 Global Status/Control Register (PCIGSCR)

31 30
R 0 0 PE
W rwc
Reset 0 0
15 14
R 0 0 PEE
W
Reset 0 0
Reg
Addr
1
Bits 29 and 28 are read-write-clear (rwc).
—Hardware can set rwc bits, but cannot clear them.
—Software can clear rwc bits that are currently set by writing a 1 to the bit location. Writing a 1 to a rwc bit that is
currently a 0 or writing a 0 to any rwc bit has no effect.
2
The reset value of bits 26-24 and 18-16 is determined by the PLL multiplier.
Bits Name
31–30 —
29 PE
28 SE
27 —
26–24 XLB2CLKIN This bit field stores the XL bus clock to external PCI clock (CLKIN)divide ratio. This field is
23–19 —
18–16 CLKINReser
ved
15–14 —
19-14
29 28 27 26
SE 0 XLB2CLKIN
1 1
rwc
0 0 0
13 12 11 10
SEE 0
0
0 0 0 0
Figure 19-9. Global Status/Control Register (PCIGSCR)
Table 19-10. PCIGSCR Field Descriptions
Reserved, should be cleared.
PERR detected. This bit is set when the PCI Parity Error line, PCIPERR, asserts (any device). A
CPU interrupt will be generated if the PCIGSCR[PEE] bit is set. It is up to application software to
clear this bit by writing '1' to it.
SERR detected. This bit is set when a PCI System Error line, PCISERR, asserts (any device). A
CPU interrupt will be generated if the PCIGSCR[SEE] bit is set. It is up to application software to
clear this bit by writing '1' to it.
Reserved, should be cleared.
read-only and the reset value is determined by the PLL multiplier (either 1, 2, or 4). Software can
read these bits to determine a valid ratio. If the register contains a differential value that does not
reflect the PLL settings, the PCI controller could malfunction.
Reserved, should be cleared.
This field is reserved.
Reserved, should be cleared.
MCF548x Reference Manual, Rev. 3
25 24 23 22
0 0
2
— 0 0
9 8 7 6
0 0 0 0
0 0 0 0
MBAR + 0xB60
Description
Section 19.5.2,
21 20 19 18
0 0 0 Reserved
0 0 0 Uninitialized
5 4 3 2
0 0 0 0
0 0 0 0
Freescale Semiconductor
17 16
1 0
0 PR
0 1