Arbiter Address Tenure Time Out Register (Xarb_Adrto) - Freescale Semiconductor MCF5480 Reference Manual

31 30 29
R 0 0 0
W
Reset 0 0 0
15 14 13
R 0 0 0
W
Reset 0 0 0
Reg
Addr
Figure 10-10. Arbiter Bus Signal Capture Register (XARB_SIGCAP)
Bits Name
31–10 —
9–7 TSIZ[0:2]
6 —
5 TBST
4–0 TT

10.3.3.7 Arbiter Address Tenure Time Out Register (XARB_ADRTO)

31 30
R 0 0
W
Reset 0 0
15 14
R
W
Reset 1 1
Reg
Addr
Figure 10-11. Arbiter Address Tenure Time Out Register (XARB_ADRTO)
10-14
28 27 26
0 0 0
0 0 0
12 11 10
0 0 0
0 0 0
Table 10-10. XARB_SIGCAP Field Descriptions
Reserved, should be cleared.
TSIZ[0:2]
Reserved, should be cleared
TBST
TT[0:4]
29 28 27 26
0 0
0 0 1 1
13 12 11 10
1 1 1 1
MCF548x Reference Manual, Rev. 3
25 24 23 22
0 0 0 0
0 0 0 0
9 8 7 6
TSIZ[0:2] —
0 0 0 0
MBAR + 0x0254
Description
25 24 23 22
ADRTO
1 1 1 1
9 8 7 6
ADRTO
1 1 1 1
MBAR + 0x0258
21 20 19 18
0 0 0 0
0 0 0 0
5 4 3 2
TBST TT[0:4]
0 0 0 0
21 20 19 18
1 1 1 1
5 4 3 2
1 1 1 1
Freescale Semiconductor
17 16
0 0
0 0
1 0
0 0
17 16
1 1
1 0
1 1