Bus Grant Mechanism - Freescale Semiconductor MCF5480 Reference Manual

Freescale semiconductor circuit board reference manual
Table of Contents

Advertisement

algorithm (LRU). Once a requesting master is identified as having priority and is granted the bus, that
master will be continue to be granted the bus if:
1. It is requesting the bus. The request must occur immediately after the required 1 clock de-assertion
after a qualified bus grant.
and
2. It is the highest priority device.
and
3. There is no address retry.
Multiple masters at level 0 will only be able to perform one tenure before the bus is passed to the next
master at level 0 using the LRU algorithm.
The priority level of each master may be changed while the arbiter is running. This allows dynamic
changes in priority such as an aging scheme. The arbiter recognizes changes after one clock.
It is possible to control priority by enabling the master priority enable bits for a master (XARB_PRIEN).
This causes the priority to be determined from the master n priority bits in the arbiter master priority
register (XARB_PRI). Once again a system dependent dynamic scheme may be employed.

10.3.2.2 Bus Grant Mechanism

10.3.2.2.1
Bus Grant
The bus grant mechanism generates the address bus grant signals to the masters using the signals from the
prioritization function. It will also generate required indicators of state to the prioritization and watchdog
functions.
The bus grant mechanism will enforce the one level address pipeline. The critical condition is that before
a third address tenure is granted, the first tenure (address and, if needed, data) must be completed. The
arbiter will assert a bus grant to a master when there are masters requesting, or if parking is enabled and
the one level pipeline condition is met.
10.3.2.2.2
Parking Modes
The bus grant mechanism will support the no parking, park on programmed master, and park on last master
bus parking modes.
When in no parking mode, the arbiter will not assert a bus grant when there are no masters asserting
a bus request.
In park on programmed master mode, the arbiter will assert a bus grant to the master indicated in
the select parked master field (ACFG[SP]) when no masters are asserting a bus request and the one
level pipeline will not be violated.
In park on last master mode, the arbiter will assert a bus grant to the last master granted the bus
when no masters are asserting a bus request and the one level pipeline will not be violated.
Freescale Semiconductor
MCF548x Reference Manual, Rev. 3
XL Bus Arbiter
10-7

Hide quick links:

Advertisement

Table of Contents
loading

This manual is also suitable for:

Mcf5481Mcf5482Mcf5483Mcf5484Mcf5485

Table of Contents