Functional Overview; Message Buffer Structure - Freescale Semiconductor MCF5480 Reference Manual

Bits Name
15–0 BUFnI
21.4

Functional Overview

The FlexCAN module is flexible in that each one of its 16 message buffers (MBs) can be assigned either
as a transmit buffer or a receive buffer. Each MB, which is up to 8 bytes long, is also assigned an interrupt
flag bit that indicates successful completion of either transmission or reception.
An arbitration algorithm decides the prioritization of MBs to be transmitted based on either the message
ID or the MB ordering. A matching algorithm makes it possible to store received frames only into MBs
that have the same ID programmed on its ID field. A masking scheme makes it possible to match the ID
programmed on the MB with a range of IDs on received CAN frames. A reception queue can be
implemented by programming the same ID on more than one receiving MB. Data coherency mechanisms
are implemented to guarantee data integrity during MB manipulation by the CPU.
Before proceeding with the functional description, an important concept must be explained. A message
buffer is said to be "active" at a given time if it can participate in the matching and arbitration algorithms
that are happening at that time. An Rx MB with a 0b0000 code is inactive (refer to
a Tx MB with a 0b1000 code is inactive (refer to
or 0b1000 will be temporarily deactivated (will not participate in the current arbitration/matching run)
when the CPU writes to the C/S field of that MB.
For both the transmit and the receive processes, the first CPU action in
preparing a MB should be to deactivate it by setting its CODE field to the
proper value. This requirement is mandatory to assure proper operation.
21.4.1

Message Buffer Structure

The message buffer structure used by the FlexCAN module is defined in the CAN Specification Version
2.0, Part B and is represented in
frames. A standard frame is represented by the 11-bit standard identifier, and an extended frame is
represented by the combined 29-bits of the standard identifier (11 bits) and the extended identifier (18
bits).
Freescale Semiconductor
Table 21-12. IFLAG Field Descriptions
IFLAG contains one interrupt flag bit per buffer. Each successful transmission/reception sets the
corresponding IFLAG bit and, if the corresponding IMASK bit is set, an interrupt request will be
generated.
To clear an interrupt flag, first read the flag as a one, and then write it as a one. Should a new flag
setting event occur between the time that the CPU reads the flag as a one and writes the flag as a
one, the flag is not cleared.
0 No such occurence.
1 The corresponding buffer has successfully completed transmission or reception.
Figure 21-12. The specification includes both standard and extended
MCF548x Reference Manual, Rev. 3
Description
Table 21-15). A MB not programmed with either 0b0000
NOTE
Functional Overview
Table 21-14). Similarly,
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