Slice Timers (Slt); Introduction; Overview; Memory Map/Register Definition - Freescale Semiconductor MCF5480 Reference Manual

Chapter 12

Slice Timers (SLT)

12.1

Introduction

This chapter explains the operation of the MCF548x slice timers.
12.1.1

Overview

Two slice timers are included to provide shorter term periodic interrupts—SLT0 and SLT1. Each timer
consists of a 32-bit counter with no prescale. The counters count down from a prescribed value and
expire/interrupt when they reach zero. They can be configured to automatically preset to the prescribed
value and resume counting or wait until the status/interrupt is serviced before beginning a new cycle.
The current count value can be read without disturbing the count operation. Each SLT has a status bit to
indicate the timer has expired. If enabled, a CPU interrupt is generated at count expiration. Each timer has
a separate interrupt. Clearing the status and/or interrupt is accomplished by writing 1 to the status bit, or
disabling the timer entirely with the timer enable (SCR[TEN]) bit.
Software should write a terminal count value of greater than 255.
12.2

Memory Map/Register Definition

There are two slice timers. Each one uses four 32-bit registers. These registers are located at an offset from
MBAR of 0x900.
Table 12-1 summarizes the SLT control registers.
Address
(MBAR +)
0x900 SLT Terminal Count Register 0
0x904
0x908 SLT Count Value Register 0
0x90C
0x910 SLT Terminal Count Register 1
0x914
0x918 SLT Count Value Register 1
0x91C
Freescale Semiconductor
Table 12-1. Slice Timer Memory Map
Name
SLT Control Register 0
SLT Status Register 0
SLT Control Register 1
SLT Status Register 1
MCF548x Reference Manual, Rev. 3
Byte 0 Byte 1 Byte 2
STCNT0
SCR0
SCNT0
SSR0
STCNT1
SCR1
SCNT1
SSR1
Byte 3 Access
R/W
R/W
R
R
R/W
R/W
R
R
12-1