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6.4 Channel Output (TO0n pin) Control
6.4.1 TO0n pin output circuit configuration
Interrupt signal of the master channel
(INTTM0n)
Interrupt signal of the slave channel
(INTTM0p)
The following describes the TO0n pin output circuit.
<1> When TOM0n = 0 (toggle mode), the set value of the TOL0n register is ignored and only INTTM0p (slave
channel timer interrupt) is transmitted to the TO0n register.
<2> When TOM0n = 1 (combination-operation mode), both INTTM0n (master channel timer interrupt) and
INTTM0p (slave channel timer interrupt) are transmitted to the TO0n register.
At this time, the TOL0n register becomes valid and the signals are controlled as follows:
When TOL0n = 0: Forward operation (INTTM0 → set, INTTM0p → reset)
When TOL0n = 1: Reverse operation (INTTM0 → reset, INTTM0p → set)
When INTTM0n and INTTM0p are simultaneously generated, (0% output of PWM), INTTM0p (reset
signal) takes priority, and INTTM0n (set signal) is masked.
<3> When TOE0n = 1, INTTM0n (master channel timer interrupt) and INTTM0p (slave channel timer interrupt)
are transmitted to the TO0n register. Writing to the TO0n register (TO0n write signal) becomes invalid.
When TOE0n = 1, the TO0n pin output never changes with signals other than interrupt signals.
To initialize the TO0n pin output level, it is necessary to set TOE0n = 0 and to write a value to TO0n.
<4> When TOE0n = 0, writing to TO0n bit to the target channel (TO0n write signal) becomes valid. When
TOE0n = 0, neither INTTM0n (master channel timer interrupt) nor INTTM0p (slave channel timer
interrupt) is transmitted to TO0n register.
<5> The TO0n register can always be read, and the TO0n pin output level can be checked.
Remarks 1. n = 0 to 6 (n = 0, 2, or 4 for master channel)
2. p = n + 1, n + 2, n + 3 ... (where p ≤ 6)
CHAPTER 6 TIMER ARRAY UNIT
Figure 6-24. Output Circuit Configuration
<1>
<2>
TOL0n
TOM0n
TOE0n
User's Manual U17854EJ9V0UD
<5>
TO0n register
Set
Reset/toggle
<3>
<4>
Internal bus
TO0n write signal
TO0n pin
209
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