Clock System Diagram; Figure 1.1 Clock System Diagram - Toshiba TXZ+ Series Reference Manual

Clock System diagram

The figure below shows a clock system diagram.
[CGWUPHCR]<WUON>
[CGWUPHCR]<WUPT[15:4]>
High speed
Warming up timer
[CGWUPHCR]
<WUCLK>
[CGOSCCR]<IHOSC1EN>
After Reset: Oscillation
f
Internal High
IHOSC1
speed ocillator1
SIWDT
FLASH
[CGOSCCR]<EOSCEN[1:0]>
After Reset: Stop
External
X2
High speed
[CGOSCCR]
X1 oscillator1
<OSCSEL>
EHCLKIN
[RLMLOSCCR]<POSCEN>
After Reset: Stop(Note)
f
Internal High
IHOSC2
OFD
speed oscillator2
LTTMR
SIWDT
[CGWUPLCR]<WULON>
[CGWUPLCR]<WUPTL[18:4]>
[R LM L OS CCR ]
<XTEN>
After Reset: Stop
Low speed
Warming up timer
External
XT2
ELOSC
Low speed
XT1
oscillator
fs
ELCLKIN
[R LM L OS CCR ]
<DRCOSCL>
Note: The state after the initialization done by the reset from the pin depends on [RLMLOSCCR]<POSCEN> setting.
fc
fc
1/2
fpll
1/4
PLL0
1/8
fc
fosc
[CGPLL0SEL]
<PLL0SEL>
1/2 1/4 1/8
[CGFCEN]
<FCIPEN23>
fosc
1/64
[CGSP CL KEN ]
<TRCKEN>
fsysh
fsysh
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Figure 1.1 Clock system diagram

13 / 88
Clock Control and Operation Mode
[CGSPCLKEN]
<ADCKEN>
ADCLK
Source clock control
[CGFCEN]
<FCIPENx>
1/16
[CGSY S CR]
<GEAR[2:0]>
[CGSYSCR]
1/16 1/32 1/64 1/128 1/256 1/512
<PRCK[3:0]>
[Peripheral function clock inputs]
RMC, CEC
[Peripheral function clock inputs]
RTC, ISD, TRGSEL
SysTick
CPU
DEBUG
TRCK TRCLKIN
1/4
（High speed system clock）
CPU, RAM0 to 2, BOOTROM,
CodeFLASH, DataFLASH, INTIF(IB,IMN)
fsysh
CG, HDMAC,SMIF,EBIF,TSPI0 to 5
[CGFSYSENA]
<IPENAx>
TXZ+ Family
TMPM4G Group(1)
ADC
DNF
（Middle speed system clock）
RAM3 to 5, BackupRAM,
FLASH(SFR), LTTMR, RLM, LVD,
INTIF(IA), RTC, ISD, RMC, CEC
UART, FUART, I2C, EI2C, TSSI,
fsysm
I2S, T32A, ADC, DAC, TSPI6 to 8,
A-PMD, PORT, TRGSEL, OFD, NBD,
SIWDT, TRM
1/2 1/4
MDMAC
[CGFSYSMENA]
<IPMENAx>
[CGFSYSMENB]
[CGEXTEND2]
[CGSYSCR]
<IPMENBx>
<RSV22[2:0]>
<MCKSEL[1:0]> [CGFSYSMENC]
<IPMENCx>
[Peripheral function prescaler inputs]
ΦT0m
（Middle speed prescaler clock)
FUART,UART, T32A
TSPI6 to 8, I2S, TSSI
1/2 1/4
[CGFSYSMENA]
<IPMENAx>
[Peripheral function prescaler inputs]
ΦT0h
（High speed prescaler clock）
TSPI0 to 5
[CGFSYSENA]
<IPENAx>
2021-06-30
fsysh
MDMACSWRST
Rev. 1.1