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Expansion Format of Extended Instructions (3)
Extended instruction
Opcode
Operand
xld.a
%rd, imm24
Example) xld.a %rd, imm24
%sp, imm24
Example) xld.a %sp, imm24
%rd, symbol±imm24
Example) xld.a %rd, symbol+imm24
%sp, symbol±imm24
Example) xld.a %sp, symbol-imm24
sadd
%rd, imm16
sadc
ssub
ssbc
Example) sadd %rd, imm16
sadd.a
%rd, imm20
ssub.a
Example) ssub.a %rd, imm20
%sp, imm20
Example) sadd.a %sp, imm20
xadd
%rd, imm16
xadc
xsub
xsbc
Example) xadc %rd, imm16
Remarks
Condition 1
imm24≤0x7f
ld.a
%rd, imm24(6:0)
imm24≤0x7f
ld.a
%sp, imm24(6:0)
Unconditional
ext
(symbol+imm24)(23:20)
ext
(symbol+imm24)(19:7)
ld.a
%rd, (symbol+imm24)(6:0)
Unconditional
ext
(symbol-imm24)(23:20)
ext
(symbol-imm24)(19:7)
ld.a
%sp, (symbol-imm24)(6:0)
imm16≤0x7f
add
%rd, imm16(6:0)
imm20≤0x7f
sub.a %rd, imm20(6:0)
imm20≤0x7f
add.a %sp, imm20(6:0)
imm16≤0x7f
adc
%rd, imm16(6:0)
Expansion format
Condition 2
0x7f<imm24≤0xfffff
ext
imm24(19:7)
ld.a
%rd, imm24(6:0)
0x7f<imm24≤0xfffff
ext
imm24(19:7)
ld.a
%sp, imm24(6:0)
–
–
0x7f<imm16
ext
imm16(15:7)
add
%rd, imm16(6:0)
0x7f<imm20
ext
imm20(19:7)
sub.a %rd, imm20(6:0)
0x7f<imm20
ext
imm20(19:7)
add.a %sp, imm20(6:0)
0x7f<imm16
ext
imm16(15:7)
adc
%rd, imm16(6:0)
Assembly Programming
Condition 3
0xfffff<imm24
ext
imm24(23:20)
ext
imm24(19:7)
ld.a
%rd, imm24(6:0)
0xfffff<imm24
ext
imm24(23:20)
ext
imm24(19:7)
ld.a
%sp, imm24(6:0)
–
–
–
–
–
–
Reference
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