Simulating Svd - Epson S5U1C17001C Manual

Cmos 16-bit single chip microcomputer, c compiler package for s1c17 family
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10.11.5 Simulating SVD

The [ES-Sim] window allows control of the supply voltage level for evaluating the SVD operation.
SVD control window
Click on the SVD control window select tab to display the SVD control window.
The SVD control window is initialized with voltage level 15 (maximum level).
Setting voltage level
The voltage level can be set within 16 steps* from 0 (low) to 15 (high) using the voltage level setting buttons.
* The number of voltage levels is equivalent to the number of valid SVD compare voltages supported in the
target model. The number of available levels may be changed depending on the model.
Clicking the button changes the current voltage level and voltage indicator bar. At the same time, the compare
voltage set in the SVD control register in the emulation memory and the voltage level set in this window are
compared and the result is written to the SVD detection result register.
SVD interrupt
If the target model supports the SVD interrupt, setting a voltage level lower than the SVD compare voltage in
this window can generate an interrupt.
S5U1C17001C ManUal
(C COMPilEr PaCkagE fOr S1C17 faMily) (Ver. 1.5.0)
Current voltage level
Voltage level setting buttons
Voltage indicator bar
SVD control window
EPSOn
10 DEBUggEr
10
Debugger
10-171

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