Epson S5U1C17001C Manual page 697

CMOS 16-bit Single Chip Microcomputer
S1C17 Family C Compiler Package
Quick Reference
for Development
Registers (S1C17 Core)
General-purpose Registers (8)
23 0
R7
R6
R5
R4
R3
R2
R1
R0
Memory Map and Trap Table (S1C17 Core)
Memory Map
0xff ffff
Reserved Core I/O area
0xff fc00
0xff fbff
0x00 0000
Special Registers (3)
23 0
PC Program counter
23 0
SP Stack pointer
7 0
PSR Processor status register
No.
0 (0x00)
1K bytes 1 (0x01)
2 (0x02)
3 (0x03)
31 (0x1f)
Internal memory/
Internal peripherals/
User area
PSR
Initial value
IL[2:0]:
IE:
Z:
N:
C:
V:
Trap Table
Vector address
Reset TTBR + 0x00
Address misaligned interrupt TTBR + 0x04
NMI TTBR + 0x08
Maskable external interrupt 3 TTBR + 0x0c
: :
Maskable external interrupt 31 TTBR + 0x7c
TTBR: Trap table start address
(Can be read from address 0xffff80.)
7 6 5 4 3 2 1
IL[2:0] IE C V Z
0 0 0 0 0 0 0
Interrupt level (0–7: Enabled interrupt level)
Interrupt enable (1: Enabled, 0: Disabled)
Zero flag (1: Zero, 0: Non zero)
Negative flag (1: Negative, 0: Positive)
Carry flag (1: Carry/borrow, 0: No carry)
Overflow flag (1: Overflow, 0: Not overflown)
S1C17 Core
:
Reference
S1C17 Core
0
N
0