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5 gnU17 iDE
When S1C17705 is selected for the target CPU device
Area
Start-end address
RAM
0x000000-0x002FBF
IO
0x004000-0x0043FF
RAM
0x004400-0x004FFF
IO
0x005000-0x0057FF
ROM
0x008000-0x087FFF
IO
0xFFFC00-0xFFFFFF
STACK
0x000000-0x002FBF
When S1C17001 is selected for the target CPU device
area
Start-end address
RAM
0x000000-0x0007BF
IO
0x004000-0x0043FF
IO
0x005000-0x005FFF
ROM
0x008000-0x00FFFF
IO
0xFFFC00-0xFFFFFF
STACK
0x000000-0x0007BF
When S1C17002 is selected for the target CPU device
area
Start-end address
RAM
0x000040-0x001FFF
IO
0x004000-0x0043FF
IO
0x004400-0x005FFF
ROM
0x020000-0x03FFFF
IO
0xFFFC00-0xFFFFFF
STACK
0x000040-0x001FFF
When S1C17003 is selected as the target CPU device
area
Start-end address
RAM
0x000000-0x000FBF
IO
0x004000-0x0043FF
IO
0x005000-0x0053BF
ROM
0x008000-0x017FFF
RAM
0x080000-0x09FFFF
IO
0xFFFC00-0xFFFFFF
STACK
0x000000-0x000FBF
When S1C17501 is selected for the target CPU device
area
Start-end address
RAM
0x000040-0x000FFF
IO
0x004000-0x0043FF
IO
0x004400-0x005FFF
RAM
0x006000-0x0067FF
ROM
0x020000-0x03FFFF
RAM
0x100000-0xFEFFFF
IO
0xFFFC00-0xFFFFFF
STACK
0x000040-0x000FFF
When S1C17602 is selected for the target CPU device
area
Start-end address
RAM
0x000000-0x000FBF
IO
0x004000-0x0043FF
IO
0x005000-0x0053BF
RAM
0x0053C0-0x0053FF
ROM
0x008000-0x017FFF
IO
0xFFFC00-0xFFFFFF
STACK
0x000000-0x000FBF
5-162
Wait states (R/W)
Access size
0/0
0/0
1/1
0/0
1/0
Halfword
0/0
–
Wait states (r/W)
access size
0/0
0/0
2/2
1/0
Halfword
0/0
–
Wait states (r/W)
access size
1/0
0/0
3/3
1/0
Halfword
0/0
-
Wait states (r/W)
access size
0/0
0/0
0/0
1/0
Halfword
1/1
0/0
-
Wait states (r/W)
access size
1/0
0/0
3/3
3/3
Halfword
1/0
Halfword
6/6
0/0
-
Wait states (r/W)
access size
0/0
0/0
2/2
0/0
Halfword
1/0
Halfword
0/0
-
EPSOn
(C COMPilEr PaCkagE fOr S1C17 faMily) (Ver. 1.5.0)
Area comment
Word
Internal RAM
Byte
Peripheral Area1
Byte
SRAM(LCD Display)
Byte
Peripheral Area2
ROM(Flash)
Byte
Reserved for Core I/O
–
Stack area
area comment
Word
Internal RAM
Byte
Peripheral Area1
Byte
Peripheral Area2
Mask ROM
Byte
Reserved for Core I/O
–
Stack area
area comment
Word
Internal RAM
Byte
Peripheral Area1
Byte
Peripheral Area2
Mask ROM
Byte
Reserved for Core I/O
-
Stack area
area comment
Word
Internal RAM
Byte
Peripheral Area1
Byte
Peripheral Area2
Mask ROM
Byte
CE0 reserved
Byte
Reserved for Core I/O
-
Stack Area
area comment
Word
Internal RAM
Byte
Peripheral Area1
Byte
Peripheral Area2
IVRAM
ROM(Flash)
Byte
SRAM
Byte
Reserved for Core I/O
-
Stack area
area comment
Word
Internal RAM
Byte
Peripheral Area1
Byte
Peripheral Area2
SRAM (LCD Display)
ROM(Flash)
Byte
Reserved for Core I/O
-
Stack Area
S5U1C17001C ManUal
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