Epson S5U1C17001C Manual page 283

[Comment:]
You can enter any comments here. Up to 255 characters can be entered. The comments entered here are
written in the parameter file.
Area list
Shows one area information in each line. Information is listed in alphabetical order, except that stack area
information is displayed collectively at the bottom of the list.
[Type]
Shows the type of area (ROM, RAM, IO, or STACK).
[Start-End Address]
Shows the start and end addresses of the area in hexadecimal notation.
[Wait R/W]
The first two single-digit values indicates the number of wait states during a read cycle (first digit) and
the number of wait states during a write cycle (second digit), respectively. The words "byte" (8 bits),
"halfword" (16 bits), and "word" (32 bits) indicate the access size in which the area is accessed. If the
rest is blank, the area is accessed in little endian mode. The areas set for big endian are marked by
"Big".
[Comments]
Shows the comment entered in each area information. You do not need to enter the symbol "#" to set off
comments.
Shown below are the contents initially set when you create a project.
When S1C17 is selected for the target CPU device
area Start-end address
RAM
0x000000–0xFFFFFF
STACK
0x000000-0x000FBF
When S1C17701 is selected for the target CPU device
area Start-end address
RAM
0x000000–0x000FBF
IO
0x004000–0x0043FF
IO
0x005000–0x005FFF
ROM
0x008000–0x017FFF
RAM
0x080000–0x08055F
IO
0xFFFC00–0xFFFFFF
STACK
0x000000-0x000FBF
When S1C17702 is selected for the target CPU device
area Start-end address
RAM
0x000000-0x002FBF
IO
0x004000-0x0043FF
IO
0x005000-0x005FFF
ROM
0x008000-0x027FFF
RAM
0x080000-0x08055F
IO
0xFFFC00-0xFFFFFF
STACK
0x000000-0x002FBF
When S1C17704 is selected for the target CPU device
area Start-end address
RAM
0x000000-0x000FBF
IO
0x004000-0x0043FF
IO
0x005000-0x005FFF
ROM
0x008000-0x017FFF
RAM
0x080000-0x08055F
IO
0xFFFC00-0xFFFFFF
STACK
0x000000-0x000FBF
S5U1C17001C ManUal
(C COMPilEr PaCkagE fOr S1C17 faMily) (Ver. 1.5.0)
Wait states (r/W) access size
0/0 word
–
Wait states (r/W) access size
0/0 word
0/0 byte
2/2 byte
0/0 halfword
1/1 byte
0/0 byte
–
Wait states (r/W) access size
0/0 Word
0/0 Byte
0/0 Byte
1/0 Halfword
1/1 Byte
0/0 Byte
–
Wait states (r/W) access size
0/0 Word
0/0 Byte
2/2 Byte
1/0 Halfword
1/1 Byte
0/0 Byte
–
EPSOn
5 gnU17 iDE
area comment
All Area
– Stack area
area comment
Internal RAM
Peripheral Area1
Peripheral Area2
ROM (Flash)
SRAM (LCD Display)
Reserved for Core I/O
– Stack area
area comment
Internal RAM
Peripheral Area1
Peripheral Area2
ROM(Flash)
SRAM(LCD Display)
Reserved for Core I/O
– Stack area
area comment
Internal RAM
Peripheral Area1
Peripheral Area2
ROM(Flash)
SRAM(LCD Display)
Reserved for Core I/O
– Stack area
5
IDE
5-161