Block Diagram - NEC mPD78F0730 Preliminary User's Manual

1.5 Block Diagram

TO00/TI010/P01
TI000/P00
RxD6/P14
TOH1/P16
TI50/TO50/P17
TI51/TO51/P33
RxD6/P14
TxD6/P13
SI10/P11
SO10/P12
SCK10/P10
RxD6/P14
INTP0/P120
INTP1/P30 to
INTP3/P32
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16-bit timer/event
counter 00
8-bit timer H1
Internal
low-speed
oscillator
Watchdog timer
8-bit timer/event
counter 50
8-bit timer/event
counter 51
Serial interface
UART6
Serial interface
CSI10
Interrupt control
3
Preliminary User's Manual U19014EJ1V0UD
CHAPTER 1 OUTLINE
78K/0
Flash
CPU
memory
core
Internal Internal
high-speed expansion
RAM RAM
V , V , FLMD0
DD SS
EV EV
DD SS
Port 0 2
P00, P01
Port 1 8
P10 to P17
4
Port 3 P30 to P33
Port 6 2
P60, P61
Port 12
3 P120-P122
Clock output
control
Power-on clear/
POC/LVI
Low voltage
control
indicator
USBP
USBM
USB
USBPUC
USBREGC
PLL
Reset control
OCD0A/X1, OCD1A/P31
On-chip debug
OCD0B/X2, OCD1B/P32
RESET
System control
X1/P121
X2/EXCLK/P122
Internal
high-speed
oscillator
Voltage regulator
REGC
17