1206 Capacitor Pad And Via Layouts - Intel Pentium III Processor 512K Design Manual

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LV Intel Pentium III Processor 512K Dual Processor Platform
highest frequency components of the current transients. To lower total board inductance and
resistance, the processor is designed with approximately 81 Vcc
Larger bulk storage (C
longer lasting changes in current demand by the component, such as coming out of an idle
condition. Similarly, they act as a storage well for current when entering an idle condition from a
running condition.
Power bypassing is required due to the relatively slow speed at which a DC-to-DC converter can
react. The loop response time of the converter feedback circuit is much longer than the time it takes
a processor load change to take effect. This is especially true if the processor load changes are
happening at a high rate. Bulk capacitance supplies energy from the time the high frequency
decoupling capacitors are drained until the power supply can react to the demand. More correctly,
the bulk capacitors in the system slow the transient requirement seen by the power source to a rate
that it is able to supply, while the high frequency capacitors slow the transient requirement seen by
the bulk capacitors to a rate that they can supply.
A load-change transient occurs when coming out of or entering a low power mode. These are not
only quick changes in current demand, but are also long lasting average current requirements.
Maintaining voltage tolerance during these changes in current requires high-density bulk
capacitors with low Effective Series Resistance (ESR) and low Effective Series Inductance (ESL).
Use thorough analysis when choosing these components.
5.4.2.1 Location of High-Frequency Decoupling
A system designer for the LV Intel Pentium
high-frequency decoupling. High-frequency decoupling should be placed as close to the power
pins of the processor as physically possible. If necessary, use both sides of the board for placing
components; this will achieve the optimum proximity to the power pins. This is vital, since the
inductance of the board's metal plane layers could cancel the usefulness of these low inductance
components.
Another method to lower the inductance that should be considered is to shorten the path from the
capacitor pads to the pins that it is decoupling. If possible, place the vias connecting to the planes
within the pad of the capacitor. If this is not possible, keep the traces as short and wide as is
feasible. Possibly one or both ends of the capacitor can be connected directly to the pin of the
processor without the use of a via. Even if simulation results look good, these practical suggestions
can be used to create an even better decoupling situation where they can be applied in layout.
Figure 20 illustrates these concepts.
Figure 20. 1206 Capacitor Pad and Via Layouts
Vias
34
), such as electrolytic (OSCON) capacitors, supply current during
BULK
Less Bad
Bad
CORE
III processor 512K should properly design for
Good
Pin
Pads
and 146 V (ground) pins.
SS
Very Good
Very Good
Capacitors
Design Guide