Veichi AC100-T3-1R5G Manual page 107

AC100 HIGH-PERFORMANCE VC INVERTER MANUAL
X8-X10 extended terminals
F2.41
trait selection
X11-X13 extended
F2.42
terminals trait selection
X8-X10 extended terminals
F2.43
on/off selection
X11-X13 extended
F2.44
terminals on/off selection
F2.45 Multifunction terminal (X8)
F2.46 Multifunction terminal (X9)
When X1 - X3 terminal input status changed after a delay time, the inverter would then regard the current input terminal
as an internal process.
X1 ~ X3 terminal
actual input status
X1 ~ X3 edge delay
input status
Note: rising edge delay time can't be greater than the actual input high pulse width time, and also the falling
delay time can't be greater than the actual low pulse width time. Otherwise there would be an invalid input
status.
F2.47 Y output delaying time
When the internal logic of the inverter operation is to change the Y terminal status, change after a set time delay after
the actual state of the output terminals Y, wherein the delay time considerations are the same as the input terminal.
Setting range:0.000-360.0s
Rising delay time
X1 ~ X3 edge delay input diagram
Setting range：0.0-360.0s
104
FUNCTION PARAMETER SPECIFICATION
Factory default: 0
falling delay time
Factory default：0