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IDEC SmartRelay functions
Timing diagram for the NAND with Edge Detection
Cycle
4.2.5
OR
Circuit diagram of a parallel circuit
with several normally open contacts:
The output status of the OR element is only 1 if at least one
input is 1, i.e. at least one of the contacts is closed.
At an unused block input (x): x = 0.
OR function logic table
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
118
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1
2
3
4
Q
1
2
3
4
5
2
3
4
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
6
7
8
9
10
Symbol in IDEC
SmartRelay:
Q
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IDEC SmartRelay Manual
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