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Core Errata
1.
Boundary Scan Is Not Fully Compliant to the IEEE 1149.1 Specification
Problem:
The IEEE Standard 1149.1 specifies the boundary scan logic to support two main goals:
1. To allow the interconnections between the various components to be tested, test data can be
shifted into all the boundary-scan register cells associated with component output pins and
loaded in parallel through the component interconnections, into those cells associated with
inputs pins; and
2. To allow the components on the board to be tested, the boundary-scan register can be used as a
means of isolating on-chip system logic from stimuli received from surrounding components,
while an internal self-test is performed. Alternatively, when the boundary-scan register is
suitably designed, it can permit a limited slow-speed static test of the on-chip system logic,
since it allows delivery of test data to the component and examination of the test results. (IEEE
std. 1149.1-1990, page 1-5)
The Intel Xscale
INTEST or RUBIST instructions. The Intel Xscale
instructions, however, since it doesn't, this makes the following statement practically invalid.
The IEEE std. 1149.1 description of the SAMPLE/PRELOAD instruction states that, "When the
SAMPLE/PRELOAD instruction is selected, the state of all signals flowing through system pins
(input or output) shall be loaded into the boundary scan register on the rising edge of the TCK in
the Capture-DR controller state." (Page 7-8).
The boundary scan cells of the Intel Xscale
driven from the on-chip system logic to the pins, when these pads are acting as outputs. This would
only be useful when trying to capture the data driven from the on-chip logic, during normal
operation of the assembled board. However, the Intel Xscale
of its clocks. Thus, even when the Intel Xscale
it would be extremely difficult (or impossible) to synch the boundary scan logic with the state of
the on-chip logic. Therefore, this feature of the boundary scan cells is not useful. This has NO
effect on the ability to determine the integrity of the interconnections on boards, which is what the
Intel Xscale
Workaround:
No workaround.
Status:
NoFix.
2.
Drain Is Not Flushed Correctly when Stalled in the Pipeline
Problem:
In a load followed by a drain scenario, the load table walks and then gets a precise data abort. The
core fetches the address for the abort handler, but in the same cycle does not flush the drain.
Implication:
Not a functional problem, but may effect performance.
Workaround:
No workaround.
Status:
NoFix.
Specification Update
®
core does not support the second goal, because it does not support the optional
®
core boundary scan logic was designed to support.
®
Intel
80219 General Purpose PCI Processor
®
core is not required to provide these
®
core bi-directional pads, do not capture the data
®
core does not allow single stepping
®
core did provide the compliant boundary scan cell,
Core Errata
13
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