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10 REAL-TIME CLOCK (RTCA)
10.3 Clock Settings
10.3.1 RTCA Operating Clock
RTCA uses CLK_RTCA, which is generated by the clock generator from OSC1 as the clock source, as its operating
clock. RTCA is operable when OSC1 is enabled.
To continue the RTCA operation during SLEEP mode with OSC1 being activated, the CLGOSC.OSC1SLPC bit
must be set to 0.
10.3.2 Theoretical Regulation Function
The time-of-day clock loses accuracy if the OSC1 frequency f
correct this error without changing any external part, RTCA provides a theoretical regulation function. Follow the
procedure below to perform theoretical regulation.
1. Measure f
and calculate the frequency tolerance correction value
OSC1
"m [ppm] = -{(f
- 32,768 [Hz]) / 32,768 [Hz]} × 10
OSC1
2. Determine the theoretical regulation execution cycle time "n seconds."
3. Determine the value to be written to the RTCACTLH.RTCTRM[6:0] bits from the results in Steps 1 and 2.
4. Write the value determined in Step 3 to the RTCACTLH.RTCTRM[6:0] bits periodically in n-second cycles us-
ing an RTCA alarm or second interrupt.
5. Monitor the RTC1S signal to check that every n-second cycle has no error included.
The correction value for theoretical regulation can be specified within the range from -64 to +63 and it should be
written to the RTCACTLH.RTCTRM[6:0] bits as a two's-complement number. Use Eq. 10.1 to calculate the cor-
rection value.
m
RTCTRM[6:0] = — — — × 256 × n
10
6
Where
n: Theoretical regulation execution cycle time [second] (time interval to write the correct value to the
RTCACTLH.RTCTRM[6:0] bits periodically via software)
m: OSC1 frequency tolerance correction value [ppm]
Figure 10.3.2.1 shows the RTC1S signal waveform.
RTC1S
RTCACTLH.RTCTRMBSY
∗ ∆T = correction time set in the RTCACTLH.RTCTRM[6:0] bits
Table 10.3.2.1 lists the frequency tolerance correction rates when the theoretical regulation execution cycle time n
is 4,096 seconds as an example.
Table 10.3.2.1 Correction Rates when Theoretical Regulation Execution Cycle Time n = 4,096 Seconds
RTCACTLH.RTCTRM[6:0]
bits (two's-complement)
0x00
0x01
0x02
0x03
· · ·
0x3e
0x3f
10-2
(However, RTCTRM[6:0] is an integer after rounding off to -64 to +63.)
Theoretical regulation execution cycle time n [s]
32,768/f
[s]
OSC1
Writing to the RTCACTLH.RTCTRM[6:0] bits
Figure 10.3.2.1 RTC1S Signal Waveform
Correction
Correction rate
value (decimal)
[ppm]
0
0.0
1
1.0
2
1.9
3
2.9
· · ·
· · ·
62
59.1
63
60.1
Minimum resolution: 1 ppm, Correction rate range: -61.0 to 60.1 ppm
Seiko Epson Corporation
has a frequency tolerance from 32.768 kHz. To
OSC1
."
6
RTCACTLH.RTCTRM[6:0]
bits (two's-complement)
value (decimal)
0x40
0x41
0x42
0x43
· · ·
0x7e
0x7f
(Eq. 10.1)
± ∆T [s]
32,768/f
OSC1
Theoretical regulation
completion interrupt
Correction
Correction rate
[ppm]
-64
-61.0
-63
-60.1
-62
-59.1
-61
-58.2
· · ·
· · ·
-2
-1.9
-1
-1.0
S1C31D41 TECHNICAL MANUAL
(Rev. 1.1)
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