Overview; Features - Epson S1C31W65 Technical Manual

1 Overview

The S1C31W65 is a 32-bit MCU with an Arm
incorporates a lot of serial interface circuits and is suitable for various kinds of battery-driven controller applications.

1.1 Features

Model
CPU
CPU
Other
Embedded Flash memory
Capacity
Erase/program count
Other
Embedded RAMs
General-purpose RAM
Display RAM
DMA Controller (DMAC)
Number of channels
Data transfer path
Transfer mode
DMA trigger source
Clock generator (CLG)
System clock source
System clock frequency (operating frequency) V
IOSC oscillator circuit (boot clock source)
OSC1 oscillator circuit
OSC3 oscillator circuit
EXOSC clock input
Other
I/O port (PPORT)
Number of general- I/O ports
purpose ports Output port
Other
Input interrupt Number of interrupt ports 56 bits (max.)
Interrupt type
Number of ports that support universal port
multiplexer (UPMUX)
Timers
Watchdog timer (WDT2)
Real-time clock (RTCA)
16-bit timer (T16)
16-bit PWM timer (T16B)
S1C31W65 TECHNICAL MANUAL
(Rev. 1.1)
Cortex -M0+ processor included that features low-power operation. It
® ®
Table 1.1.1 Features
Arm ® 32-bit RISC processor Cortex
Serial-wire debug ports (SW-DP) and a micro trace buffer (MTB) included
128K bytes (for both instructions and data)
1,000 times (min.) * When being programmed by the dedicated flash loader
On-board programming function
Flash programming voltage can be generated internally.
16K bytes (shared with MTB)
112 bytes
4 channels
Memory to memory, memory to peripheral, and peripheral to memory
Basic, ping-pong, scatter-gather
UART3, SPIA, I2C, T16B, SNDA, ADC12A, and software
4 sources (IOSC/OSC1/OSC3/EXOSC)
voltage mode = mode0: 33 MHz (max.)
D1
V voltage mode = mode1: 2.16 MHz (max.)
D1
V voltage mode = mode0: 32/24/16/12/8/2/1 MHz (typ.) selectable embedded oscillator
D1
V voltage mode = mode1: 2/1 MHz (typ.) selectable embedded oscillator
D1
2 µs (max.) starting time (time from cancelation of SLEEP state to vector table read
by the CPU when the system clock = 32 MHz)
32.768 kHz (typ.) crystal oscillator
32 kHz (typ.) embedded oscillator
Oscillation stop detection circuit included
33 MHz (max.) crystal/ceramic oscillator
32/24/16/12/8 MHz (typ.) selectable embedded oscillator
33 MHz (max.) square or sine wave input
Configurable system clock division ratio
Configurable system clock used at wake up from SLEEP state
Operating clock frequency for the CPU and all peripheral circuits is selectable.
63 bits (max.)
1 bit
Pins are shared with the peripheral I/O.
Rising edge interrupts and falling edge interrupts can be enabled individually.
32 bits
A peripheral circuit I/O function selected via software can be assigned to each port.
Generates NMI or watchdog timer reset.
Programmable NMI/reset generation cycle
128–1 Hz counter, second/minute/hour/day/day of the week/month/year counters
Theoretical regulation function for 1-second correction
Alarm and stopwatch functions
8 channels
Generates the SPIA master clock and the ADC12A trigger signal.
3 channels
Event counter/capture function
PWM waveform generation function
Number of PWM output or capture input ports: 4 ports/channel
Seiko Epson Corporation
S1C31W65
® -M0+
1 OVERVIEW
1-1