Samsung S5PC100 User Manual page 1746

KEYPAD INTERFACE
2 DEBOUNCING FILTER
The debouncing filter is supported for keypad interrupt of any key input. The filtering width is approximately
62.5usec ("FCLK" two-clock, if the FCLK is 32kHz). The keypad interrupt (key pressed or key released) to the
CPU is an ANDed signal of all row input lines after filtering.
FILTER_IN
FILTER_OUT
Filter width : 2 FCLK
Filter Clock(FCLK) is a FLT_CLK or the division of that clock.
FLT_CLK is come from System Controller, OSC_IN or USB_XTI.
3 FILTER CLOCK
KEYPAD interface debouncing filter clock (FCLK) is divided from FLT_CLK that is OSC_IN. You can set compare
value for 10-bit up-counter (KEYIFFC). If filter enable bit (FC_EN) is HIGH, filter clock divider is ON. The
frequency of FCLK is frequency of FLT_CLK / ((KEYIFFC + 1) x 2). On the contrary FC_EN is Low, filter clock
divider does not divide FLT_CLK.
4 WAKEUP SOURCE
If the Key input is used to wakeup source from IDLE, STOP or SLEEP mode, KEYPAD I/F register setting is not
required. GPIO register setting (GPH2CON, GPH3CON) for KEYPAD I/F and SYSCON register (PWR_CFG) to
mask are required for wakeup.
10.8-2
Filter width
Figure 10.8-2 Internal Debouncing Filter Operation
S5PC100 USER'S MANUAL (REV1.0)
Filter width Filter width