Samsung S5PC100 User Manual page 1796

S5PC100 USER'S MANUAL (REV1.0)
4.2 DMA AND INTERRUPT CONFIGURATION REGISTER
4.2.1 DMA and Interrupt Configuration Control/Status Register. (DnI_Cfg, R/W, Address = 0xF400_0000)
DnI_Cfg
WrPrivMismatch
RdPrivMismatch
Reserved
SHA_intr_Status
DES_intr_Status
AES_intr_Status
Reserved
FTx_intr_Status
FRx_intr_Status
Reserved
SHA_intr_En
DES_intr_En
AES_intr_En
Reserved
FTx_intr_En
FRx_intr_En
Reserved
TxTrgLevel
TxDmaEnb
Reserved
RxTrgLevel
RxDmaEnb
Note: 1. The SHA-1 related modules(HMAC, SHA-1, and PRNG) do not support 24-word trigger level setting
(DnI_Cfg[2:1], DnI_Cfg[6:5]).
2. The SECSS interrupt must be masked in case of SECSS DMA mode operation.
3. The SECSS does not recommend SECSS interrupt mode instead of polling mode in case of SECSS
FiFo mode operation.
Bit
SFR Write Access Privilege Mismatch Status bit. If set to '1',
[31]
SFR Write Access Privilege Mismatch occurs.
SFR Read Access Privilege Mismatch Status bit. If set to '1',
[30]
SFR Read Access Privilege Mismatch occurs.
[29:23] Reserved
[22] SHA-1/PRNG interrupt status (Resets to 0 if read).
[21] DES/TDES interrupt status (Resets to 0 if read).
[20] AES interrupt status (Resets to 0 if read).
[19:18] Reserved
[17] FIFO-Tx interrupt status (Resets to 0 if read).
[16] FIFO-Rx interrupt status (Resets to 0 if read).
[15] Reserved
[14] SHA-1/PRNG interrupt enabled
[13] DES/TDES interrupt enabled
[12] AES interrupt enabled
[11:10] Reserved
[9] FIFO-Tx interrupt enabled
[8] FIFO-Rx interrupt enabled
[7] Reserved
[6:5] Tx side DMA trigger level setting.
00 = 8-word
01 = 16-word
10 = 24-word
11 = Reserved
[4] Tx side DMA enable bit (1= Enable)
[3] Reserved
Rx side DMA trigger level setting.
00 = 8-word
[2:1] 01 = 16-word
10 = 24-word
11 = Reserved
[0] Rx side DMA enable bit (1= Enable)
Description
CRYPTO ENGINE BLOCK
Reset Value
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
2'b00
1'b0
2'b00
1'b0
11.3-17