SMART Embedded Computing MVME2502 Manuals

Manuals and User Guides for SMART Embedded Computing MVME2502. We have 2 SMART Embedded Computing MVME2502 manuals available for free PDF download: Installation And User Manual, Installation And Use Manual

SMART Embedded Computing MVME2502 Installation And User Manual (150 pages)

Brand: SMART Embedded Computing | Category: Computer Hardware | Size: 1.22 MB

Table of Contents
3
About this Manual
13
Safety Notes
19
Sicherheitshinweise
23
Introduction
27
Overview
27
Standard Compliances
29
Mechanical Data
29
Table 1-1 Board Standard Compliances
29
Table 1-2 Mechanical Data
29
Ordering Information
30
Product Identification
30
Figure 1-1 Serial Number Location-ENP1 Variant
30
Figure 1-2 Serial Number Location-ENP2 Variant
31
Hardware Preparation and Installation
33
Overview
33
Unpacking and Inspecting the Board
34
Requirements
34
Environmental Requirements
35
Table 2-1 Environmental Requirements
35
Power Requirements
36
Table 2-2 Power Requirements
36
Equipment Requirements
37
Configuring the Board
37
Installing Accessories
38
Rear Transition Module
38
PMC/XMC Support
39
Installation of MVME2502-HDMNTKIT1/MVME2502-HDMNTKIT2
40
Installing and Removing the Board
43
Completing the Installation
44
Controls, Leds, and Connectors
45
Board Layout
45
Figure 3-1 Board Layout ENP1 Variant
45
Figure 3-2 Board Layout ENP2 Variant
46
Front Panel
47
Figure 3-3 Front Panel Leds, Connectors and Switches
47
Reset Switch
48
Leds
48
Front Panel Leds
48
Figure 3-4 Front Panel Leds
48
Table 3-1 Front Panel Leds
48
On-Board Leds
50
Figure 3-5 On-Board Leds
50
Table 3-2 On-Board Leds Status
50
Connectors
51
Front Panel Connectors
51
RJ-45 with Integrated Magnetics
51
Table 3-3 Ethernet Tri-Speed RJ-45 Connectors (GENET1 and GENET2)
51
Front Panel Serial Port (COM1)
52
USB Connector
52
Table 3-4 Front Panel Serial Port
52
Table 3-5 USB Connector
52
Vmebus P1 Connector
53
Table 3-6 Vmebus P1 Connector
53
Vmebus P2 Connector
54
Table 3-7 Vmebus P2 Connector
54
On-Board Connectors
56
SATA Connector (J3)
56
Table 3-8 Custom SATA Connector (J3)
56
PMC Connectors
57
Table 3-9 PMC J11/J111 Connector
57
Table 3-10 PMC J12/J222 Connector
59
Table 3-11 PMC J13/J333 Connector
60
Table 3-12 PMC J14 Connector
61
JTAG Connector (P6)
63
Table 3-13 JTAG Connector (P6)
63
COP Connector P50(15)
64
Table 3-14 COP Header (P50)
64
XMC Connector (XJ1)
65
Table 3-15 XMC Connector (XJ1) Pin out
65
XMC Connector (XJ2)
67
Miscellaneous P2020 Debug Connectors(P4)
67
Table 3-16 XMC Connector (XJ2) Pin out
67
Switches
68
Geographical Address Switch (S1)
68
Table 3-17 P2020 Debug Header (P4)
68
Figure 3-6 Geographical Address Switch
69
Table 3-18 Geographical Address Switch
69
SMT Configuration Switch (S2)
70
Figure 3-7 SMT Configuration Switch Position
70
Table 3-19 SMT Configuration Switch Settings
70
Functional Description
73
Block Diagram
73
Figure 4-1 Block Diagram
73
Chipset
74
E500 Processor Core
74
Integrated Memory Controller
74
PCI Express Interface
75
Local Bus Controller (LBC)
75
Secure Digital Host Controller (SDHC)
75
I2C Interface
75
USB Interface
76
Duart
76
DMA Controller
76
Enhanced Three-Speed Ethernet Controller (Etsec)
76
General Purpose I/O (GPIO)
76
Table 4-1 P2020 GPIO Functions
76
Security Engine (SEC) 3.1
77
Common On-Chip Processor (COP)
78
P2020 Strapping Pins
78
Table 4-2 P2020 Strapping Options
78
System Memory
81
Timers
81
Real Time Clock
81
P2020 Internal Timer
81
Watchdog Timer
81
CPLD Tick Timer
81
Ethernet Interfaces
82
SPI Bus Interface
82
Table 4-3 Ethernet Port Device Names
82
SPI Flash Memory
83
SPI Flash Programming
83
Firmware Redundancy
83
Crisis Recovery
84
Figure 4-2 SPI Device Multiplexing Logic
84
Front UART Control
85
Rear UART Control
85
PMC/XMC Sites
86
PMC Add-On Card
87
XMC Add-On Card
87
SATA Interface
87
VME Support
87
Tsi148 VME Controller
88
Usb
88
I2C Devices
88
Reset/Control CPLD
89
Table 4-4 P2020 I 2 C Port1 Devices
89
Table 4-5 P2020 I 2 C Port2 Devices
89
Power Management
90
On-Board Voltage Supply Requirement
90
Power up Sequencing Requirements
90
Table 4-6 Voltage Supply Requirement
90
Clock Structure
91
Figure 4-3 Clock Distribution Diagram
91
Reset Structure
92
Reset Sequence
92
Thermal Management
92
Real-Time Clock Battery
92
Table 4-7 Thermal Interrupt Threshold
92
Debugging Support
93
POST Code Indicator
93
JTAG Chain and Board
93
Table 4-8 POST Code Indicator on the LED
93
Custom Debugging
94
Figure 4-4 JTAG Chain Diagram
94
Rear Transition Module (RTM)
95
Figure 4-5 RTM Block Diagram
95
Table 4-9 Transition Module Features
95
Memory Maps and Registers
97
Overview
97
Memory Map
97
Table 5-1 Physical Address Map
97
Flash Memory Map
98
Linux Devices Memory Map
98
Table 5-3 Linux Devices Memory Map
99
Programmable Logic Device (PLD) Registers
100
PLD Revision Register
100
PLD Year Register
100
Table 5-4 PLD Revision Register
100
Table 5-5 PLD Year Register
100
PLD Month Register
101
PLD Day Register
101
Table 5-6 PLD Month Register
101
Table 5-7 PLD Day Register
101
PLD Sequence Register
102
PLD Power Good Monitor Register
102
Table 5-8 PLD Sequence Register
102
Table 5-9 PLD Power Good Monitor Register
102
PLD LED Control Register
103
PLD PCI/PMC/XMC (Slot1) Monitor Register
103
Table 5-10 PLD LED Control Register
103
Table 5-11 PLD PCI/PMC/XMC (Slot1) Monitor Register
103
PLD PCI/PMC/XMC (Slot2) Monitor Register
104
Table 5-12 PLD PCI/PMC/XMC (Slot2) Monitor Register
104
PLD U-Boot and TSI Monitor Register
105
Table 5-13 PLD U-Boot and TSI Monitor Register
105
PLD Boot Bank Register
106
Table 5-14 PLD Boot Bank Register
106
PLD Write Protect and I C Debug Register
107
Table 5-15 PLD Write Protect and I C Debug Register
107
PLD Test Register 1
108
Table 5-16 PLD Test Register 1
108
PLD Test Register 2
109
PLD GPIO2 Interrupt Register
109
Table 5-17 PLD Test Register 2
109
Table 5-18 PLD GPIO2 Interrupt Register
109
PLD Shutdown and Reset Control and Reset Reason Register
110
Table 5-19 PLD Shutdown and Reset Control and Reset Reason Register
110
EMMC Reset Register
111
Table 5-20 PLD Shutdown and Reset Control and Reset Reason Register
111
PLD Watchdog Timer Refresh Register
112
PLD Watchdog Control Register
112
Table 5-21 PLD Watchdog Timer Refresh Register
112
Table 5-22 PLD Watchdog Control Register
112
PLD Watchdog Timer Count Register
113
PLD Watchdog Timer Count Value Register
113
Table 5-23 PLD Watchdog Timer Count Register
113
Table 5-24 PLD Watchdog Timer Count Register
113
External Timer Registers
114
Prescaler Register
114
Table 5-25 Prescaler Register
114
Control Registers
115
Compare High and Low Word Registers
115
Table 5-26 Control Registers
115
Table 5-27 Compare High Word Registers
116
Table 5-28 Compare Low Word Registers
116
Counter High and Low Word Registers
117
Table 5-29 Counter High Word Registers
117
Table 5-30 Counter Low Word Registers
117
Boot System
119
Overview
119
Accessing U-Boot
119
Boot Options
120
Booting from a Network
120
Booting from an Optional SATA Drive
121
Booting from a USB Drive
121
Booting from an SD Card
122
Booting Vxworks through the Network
122
Using the Persistent Memory Feature
123
MVME2502 Specific U-Boot Commands
124
Table 6-1 MVME2502 Specific U-Boot Commands
124
Updating U-Boot
127
Programming Model
129
Overview
129
Reset Configuration
129
Table 7-1 por Configuration Settings
129
Interrupt Controller
133
Table 7-2 MVME2502 Interrupt List
133
I 2 C Bus Device Addressing
134
Table 7-3 C Bus Device Addressing
134
Ethernet PHY Address
135
Other Software Considerations
135
Mram
135
Real Time Clock
135
Quad UART
135
Table 7-4 PHY Types and MII Management Bus Address
135
LBC Timing Parameters
136
Table 7-5 LBC Timing Parameters
136
Clock Distribution
137
Table 7-6 Clock Distribution
137
System Clock
138
Real Time Clock Input
138
Table 7-7 System Clock
138
Local Bus Controller Clock Divisor
139
Replacing the Battery
141
Figure A-1 Battery Location ENP1 Variant
141
Figure A-2 Battery Location ENP2 Variant
142
Related Documentation
145
Penguin Solutions Documentation
145
Manufacturers' Documents
145
Table B-1 Penguin Edge Documentation
145
Table B-2 Manufacturers' Publications
145
Related Specifications
146
Table B-3 Related Specifications
146

SMART Embedded Computing MVME2502 Installation And Use Manual (144 pages)

Brand: SMART Embedded Computing | Category: Desktop | Size: 1.22 MB

Table of Contents
3
About this Manual

13
Safety Notes

19
Sicherheitshinweise

23
1 Introduction

27
2 Hardware Preparation and Installation

33
- Overview
  33
- Unpacking and Inspecting the Board
  34
- Requirements
  34
  - Environmental Requirements
    35
  - Power Requirements
    36
  - Table 2-2 Power Requirements
    36
  - Equipment Requirements
    37
- Configuring the Board
  37
- Installing Accessories
  38
- Installing and Removing the Board
  43
- Completing the Installation
  44
3 Controls, Leds, and Connectors

45
- Board Layout
  45
- Figure 3-1 Board Layout ENP1 Variant
  45
- Figure 3-2 Board Layout ENP2 Variant
  46
- Front Panel
  47
  - Figure 3-3 Front Panel Leds, Connectors and Switches
    47
  - Reset Switch
    48
- Leds
  48
  - Front Panel Leds
    48
  - Figure 3-4 Front Panel Leds
    48
  - Table 3-1 Front Panel Leds
    48
  - On-Board Leds
    50
  - Figure 3-5 On-Board Leds
    50
  - Table 3-2 On-Board Leds Status
    50
- Connectors
  51
  - Front Panel Connectors
    51
    
    With Integrated Magnetics (J1)
    51
    
    Table 3-3 Front Panel Tri-Speed Ethernet Connector (J1)
    51
    
    Front Panel Serial Port (J4)
    52
    
    Table 3-4 Front Panel Serial Port (J4)
    52
    
    USB Connector (J5)
    53
    
    Vmebus P1 Connector
    53
    
    Table 3-5 USB Connector (J5)
    53
    
    Table 3-6 Vmebus P1 Connector
    53
    
    Vmebus P2 Connector
    55
    
    Table 3-7 Vmebus P2 Connector
    55
  - On-Board Connectors
    56
    
    SATA Connector (J3)
    56
    
    Table 3-8 Custom SATA Connector (J3)
    56
    
    PMC Connectors
    57
    
    Table 3-9 PMC J11/J111 Connector
    57
    
    Table 3-10 PMC J12/J222 Connector
    59
    
    Table 3-11 PMC J13/J333 Connector
    60
    
    Table 3-12 PMC J14 Connector
    61
    
    JTAG Connector (P6)
    63
    
    Table 3-13 JTAG Connector (P6)
    63
    
    COP Connector P50(15)
    64
    
    Table 3-14 COP Header (P50)
    64
    
    XMC Connector (XJ1)
    65
    
    Table 3-15 XMC Connector (XJ1) Pin out
    65
    
    XMC Connector (XJ2)
    66
    
    Miscellaneous P2020 Debug Connectors(P4)
    66
    
    Table 3-16 XMC Connector (XJ2) Pin out
    66
- Switches
  67
4 Functional Description

71
- Block Diagram
  71
- Figure 4-1 Block Diagram
  71
- Chipset
  72
  - E500 Processor Core
    72
  - Integrated Memory Controller
    72
  - PCI Express Interface
    73
  - Local Bus Controller (LBC)
    73
  - Secure Digital Host Controller (SDHC)
    73
  - I2C Interface
    73
  - USB Interface
    74
  - Duart
    74
  - DMA Controller
    74
  - Enhanced Three-Speed Ethernet Controller (Etsec)
    74
  - General Purpose I/O (GPIO)
    74
  - Table 4-1 P2020 GPIO Functions
    74
  - Security Engine (SEC) 3.1
    75
  - Common On-Chip Processor (COP)
    76
  - P2020 Strapping Pins
    76
  - Table 4-2 P2020 Strapping Options
    76
- System Memory
  79
- Timers
  79
  - Real Time Clock
    79
  - P2020 Internal Timer
    79
  - Watchdog Timer
    79
  - CPLD Tick Timer
    79
- Ethernet Interfaces
  80
- SPI Bus Interface
  80
  - SPI Flash Memory
    80
  - SPI Flash Programming
    81
  - Firmware Redundancy
    81
  - Crisis Recovery
    82
  - Figure 4-2 SPI Device Multiplexing Logic
    82
- Front UART Control
  83
- Rear UART Control
  83
- PMC/XMC Sites
  84
  - PMC Add-On Card
    85
  - XMC Add-On Card
    85
- SATA Interface
  85
- 4.11 VME Support
  85
  - 4.11.1 Tsi148 VME Controller
    86
- Usb
  86
- I2C Devices
  86
- Reset/Control CPLD
  87
- Table 4-3 P2020 I 2 C Port1 Devices
  87
- Table 4-4 P2020 I 2 C Port2 Devices
  87
- Power Management
  88
- Clock Structure
  89
- Figure 4-3 Clock Distribution Diagram
  89
- Reset Structure
  90
  - Reset Sequence
    90
- 4.18 Thermal Management
  90
- Real-Time Clock Battery
  90
- Table 4-6 Thermal Interrupt Threshold
  90
- Debugging Support
  91
  - POST Code Indicator
    91
  - JTAG Chain and Board
    91
  - Table 4-7 POST Code Indicator on the LED
    91
  - Custom Debugging
    92
  - Figure 4-4 JTAG Chain Diagram
    92
- Rear Transition Module (RTM)
  93
- Figure 4-5 RTM Block Diagram
  93
- Table 4-8 Transition Module Features
  93
5 Memory Maps and Registers

95
- Overview
  95
- Memory Map
  95
- Table 5-1 Physical Address Map
  95
- Flash Memory Map
  96
- Linux Devices Memory Map
  96
- Table 5-2 Flash Memory Map
  96
- Table 5-3 Linux Devices Memory Map
  97
- Programmable Logic Device (PLD) Registers
  98
  - PLD Revision Register
    98
  - PLD Year Register
    98
  - Table 5-4 PLD Revision Register
    98
  - Table 5-5 PLD Year Register
    98
  - PLD Month Register
    99
  - PLD Day Register
    99
  - PLD Sequence Register
    99
  - Table 5-6 PLD Month Register
    99
  - PLD Power Good Monitor Register
    100
  - PLD LED Control Register
    100
  - PLD PCI/PMC/XMC (Slot1) Monitor Register
    101
  - PLD PCI/PMC/XMC (Slot2) Monitor Register
    102
  - PLD U-Boot and TSI Monitor Register
    103
  - PLD Boot Bank Register
    103
  - PLD Write Protect and I C Debug Register
    104
  - PLD Test Register 1
    105
  - PLD Test Register 2
    106
  - PLD GPIO2 Interrupt Register
    106
  - PLD Shutdown and Reset Control and Reset Reason Register
    107
  - EMMC Reset Register
    108
  - PLD Watchdog Timer Refresh Register
    109
  - PLD Watchdog Control Register
    109
  - PLD Watchdog Timer Count Register
    110
  - PLD Watchdog Timer Count Value Register
    110
- External Timer Registers
  111
  - Prescaler Register
    111
  - Control Registers
    112
  - Compare High and Low Word Registers
    112
  - Counter High and Low Word Registers
    114
6 Boot System

115
- Overview
  115
- Accessing U-Boot
  115
- Boot Options
  116
  - Booting from a Network
    116
  - Booting from an Optional SATA Drive
    117
  - Booting from a USB Drive
    117
  - Booting from an SD Card
    118
  - Booting Vxworks through the Network
    118
- Using the Persistent Memory Feature
  119
- MVME2502 Specific U-Boot Commands
  120
- Updating U-Boot
  123
7 Programming Model

125
- Overview
  125
- Reset Configuration
  125
- Interrupt Controller
  129
- I 2 C Bus Device Addressing
  130
- Ethernet PHY Address
  131
- Other Software Considerations
  131
  - Mram
    131
  - Real Time Clock
    131
  - Quad UART
    131
  - LBC Timing Parameters
    132
- Clock Distribution
  133
  - System Clock
    134
  - Real Time Clock Input
    134
  - Local Bus Controller Clock Divisor
    134
Replacing the Battery

135
- Figure A-1 Battery Location ENP1 Variant
  135
- Figure A-2 Battery Location ENP2 Variant
  136
Related Documentation

139
- SMART Embedded Computing Documentation
  139
- Manufacturers' Documents
  139
- Related Specifications
  140

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SMART Embedded Computing MVME2502 Manuals

SMART Embedded Computing MVME2502 Installation And User Manual (150 pages)

Table of Contents

SMART Embedded Computing MVME2502 Installation And Use Manual (144 pages)

Table of Contents

About this Manual

Safety Notes

Sicherheitshinweise

1 Introduction

2 Hardware Preparation and Installation

3 Controls, Leds, and Connectors

4 Functional Description

5 Memory Maps and Registers

6 Boot System

7 Programming Model

Replacing the Battery

Related Documentation

Related Products

SMART Embedded Computing Categories