Lbc Timing Parameters - SMART Embedded Computing MVME2502 Installation And Use Manual

Programming Model
7.6.4

LBC Timing Parameters

The following table defines the timing parameters for the devices on the local bus.
Table 7-5
BCTLD
CSNT
ACS
XACS
SCY
SETA
TRLX
EHTR
EAD
Field Description
BCTLD
CSNT
ACS
XACS
SCY
SETA
TRLX
132
LBC Timing Parameters
0 1
MRAM UART 0
0 0
1 1
10 10
0 0
0011 0011
0 0
0 0
0 0
0 0
Buffer control disable.
0 - LBCTL is asserted upon access to the current memory bank.
Chip Select negation time.
1 - LCSn and LWE are negated one quarter of the bus clock cycle earlier
Address to chip-select setup.
10 - LCSn is outputted one quarter bus clock cycle after the address lines.
Extra Address to chip-select setup
0 - Address to chip-select setup is determined by ORx[ACS]
Cycle length in bus clocks
0011 - bus clock cycle wait state
External address termination
0 - Access is terminated internally by the memory controller unless
the external device asserts LGTA earlier to terminate the access.
Timing Relaxed
0 - Normal timing is generated by the GPCM.
2 3
UART 1 UART 2
0 0
1 1
10 10
0 0
0011 0011
0 0
0 0
0 0
0 0
MVME2502 Installation and Use (6806800R96G)
Programming Model
4 5
UART 3 CPLD
0 0
1 1
10 10
0 0
0011 0011
0 0
0 0
0 0
0 0
6
Timers
0
1
10
0
0011
0
0
0
0