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5.5.14
PLD Test Register 2
The MVME2502 PLD provides an 8-bit general purpose read/write register which is used
by the software for PLD testing or general status bit storage.
Table 5-17 PLD Test Register 2
REG
Bit
Field
OPER
RESET
Field Description
TEST_REG2
5.5.15
PLD GPIO2 Interrupt Register
The abort switch, Tick Timer 0, 1 and 2 interrupts are ORed together. The MVME2502
provides an interrupt register that the system software reads to determine which device the
interrupt originated from. GPIO2 will be driven low if any of the interrupts asserts.
Table 5-18 PLD GPIO2 Interrupt Register
REG
Bit
Field
OPER
RESET
Field Description
CPU_RTC_SEL
SW2-3
MVME2502 Installation and Use (6806800R96L)
PLD Write Protect I2C Debug- 0xFFDF0095
7
6
5
TEST_REG1
R/W
00
General purpose 8-bit R/W field
PLD Write Protect I2C Debug- 0xFFDF0095
7
6
5
CPU_RT
SW2-3
RSVD
C_SEL
R
0
0
X
CPU RTC Input Select
0-1.824MHz (default)
1-SQW/INTB from DS1337 RTC
SW2-3 state (User defined)
0-SW2-3 closed
1-SW2-3 open (default)
Memory Maps and Registers
4
3
2
4
3
2
RSVD
NMI
TICK0_INT TICK1_INT TICK2_INT
0
0
0
1
0
1
0
0
0
109
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