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Memory Maps and Registers
Field Description
MUX1_SEL_SW
SW2-4
PMC1_EREADY
PMC1P_N
XMCP1_N
PCI1_PCIXCAP
5.5.9
PLD PCI/PMC/XMC (Slot2) Monitor Register
The MVME2502 PLD provides an 8-bit register which indicates the status of the
SATA/PMC/XMC interface signals.
Table 5-12 PLD PCI/PMC/XMC (Slot2) Monitor Register
REG
Bit
Field
OPER
RESET
104
Select for PCIe MUX1 (R/W)
1 - PMC
0 - XMC
SW2-4 state (User defined)
0 - SW2-4 closed
1 - SW2-4 open (default)
Indicates PCI device is ready for enumeration
1 - PMC ready for enumeration
0 - PMC is not ready for enumeration
PMC Presence Indicator
1 - PMC is not present
0 - PMC is present
XMC Presence Indicator
1 - XMC is not present
0 - XMC is present
PCI Capability Indicator
1 - PCI-X capable
0 - PCI capable
PLD PCI_PMC_XMC_MNTR - 0xFFDF001F
7
6
5
SD1_MU
SD1_MU
SW2-4
X_SEL1
X_SEL0
R
X
X
X
4
3
2
SATA0_
PMC2_E
PMC2P_
DETECT
READY
N
_N
X
X
X
MVME2502 Installation and Use (6806800R96L)
Memory Maps and Registers
1
0
XMCP2_
PMC2_P
N
CIXCAP
X
X
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