Pld U-Boot And Tsi Monitor Register; Table 5-13 Pld U-Boot And Tsi Monitor Register - SMART Embedded Computing Penguin Edge MVME250 Series Installation And User Manual

Field Description
SD1_MUX_SEL[1:0]
SW2-4
PMC2_EREADY
SATA0_DETECT_N
PMC2P_N
XMCP2_N
PMC2_PCIXCAP
5.5.10

PLD U-Boot and TSI Monitor Register

The MVME2502 PLD provides an 8-bit register which indicates the status of the U-Boot's
normal environment switch and TSI interface signals.

Table 5-13 PLD U-Boot and TSI Monitor Register

REG
Bit
Field
OPER
RESET 0
MVME2502 Installation and Use (6806800R96L)
Select for PCIe MUX1 (Read Only)
11 - XMC (default)
10 - PMC
01-SATA
00-Unused
SW2-4 state (User defined)
0 - SW2-4 closed
1 - SW2-4 open (default)
Indicates PCI device is ready for enumeration
1 - PMC ready for enumeration
0 - PMC is not ready for enumeration
SATA drive presence indicator
1-SATA not present
0-SATA present
PMC Presence Indicator
1 - PMC is not present
0 - PMC is present
XMC Presence Indicator
1 - XMC is not present
0 - XMC is present
PCI Capability Indicator
1 - PCI-X capable
0 - PCI capable
PLD PCI_PMC_XMC_MNTR - 0xFFDF001E
7 6 5
RSVD RSVD RSVD
R
0 0
Memory Maps and Registers
4 3 2
RSVD RSVD BDFAIL_N NORMAL_ENV
0 0 X
1 0
SCON
X X
105