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5.5.10
PLD U-Boot and TSI Monitor Register
The MVME2502 PLD provides an 8-bit register which indicates the status of the U-Boot's
normal environment switch and TSI interface signals.
Table 5-13
REG
Bit
Field
OPER
RESET 0
Field Description
BDFAIL_N
NORMAL_ENV
SCON
5.5.11
PLD Boot Bank Register
The MVME2502 PLD provides an 8-bit register which is used to declare successful U-Boot
loading, indicating the SPI boot bank priority and actual SPI bank it booted from.
Table 5-14
REG
Bit
Field
OPER
RESET
MVME2502 Installation and Use (6806800R96G)
PLD U-Boot and TSI Monitor Register
PLD PCI_PMC_XMC_MNTR - 0xFFDF001E
7
6
5
RSVD
RSVD
RSVD
R
0
0
TSI148 BDFAIL_N Pin out
1 - No TSI Fail
0 - TSI Fail
Normal Environment Switch Indicator
1 - Use safe ENV
0 - Use normal ENV
System Controller Indicator
1 - System Controller
0 - Non-system Controller
PLD Boot Bank Register
PLD Boot Bank - 0xFFDF0050
7
6
5
SPI_GOODReg
(write 0xA4 into this reg to indicate successful loading of the U-
Boot.
R/W
0
0
0
Memory Maps and Registers
4
3
2
RSVD
RSVD
BDFAIL_N NORMAL_ENV
0
0
X
4
3
0
0
1
0
SCON
X
X
2
1
0
BOOT_B
BOOT_S
LOCK_A
PI
R
R
0
X
0
103
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