Pld Boot Bank Register; Table 5-14 Pld Boot Bank Register - SMART Embedded Computing Penguin Edge MVME250 Series Installation And User Manual

Memory Maps and Registers
Field Description
BDFAIL_N
NORMAL_ENV
SCON
5.5.11

PLD Boot Bank Register

The MVME2502 PLD provides an 8-bit register which is used to declare successful U-Boot
loading, indicating the SPI boot bank priority and actual SPI bank it booted from.

Table 5-14 PLD Boot Bank Register

REG
Bit
Field
OPER
RESET
Field Description
BOOT_BLOCK_A
BOOT_SPI
106
TSI148 BDFAIL_N Pin out
1 - No TSI Fail
0 - TSI Fail
Normal Environment Switch Indicator
1 - Use safe ENV
0 - Use normal ENV
System Controller Indicator
1 - System Controller
0 - Non-system Controller
PLD Boot Bank - 0xFFDF0050
7 6 5
SPI_GOODReg
(write 0xA4 into this reg to indicate successful loading of the U-
Boot.
R/W
0 0 0
Boot Block Manual Selector Switch
1 - SPI0
0 - SPI1
Actual Boot Bank
1 - SP1
0 - SPI0
4 3 2
0 0 0
MVME2502 Installation and Use (6806800R96L)
Memory Maps and Registers
1 0
BOOT_B BOOT_S
LOCK_A PI
R R
X 0