Pld Watchdog Timer Refresh Register; Pld Watchdog Control Register; Table 5-21 Pld Watchdog Timer Refresh Register; Table 5-22 Pld Watchdog Control Register - SMART Embedded Computing Penguin Edge MVME250 Series Installation And User Manual

Memory Maps and Registers
5.5.18

PLD Watchdog Timer Refresh Register

The MVME2502 provides a watchdog timer refresh register.

Table 5-21 PLD Watchdog Timer Refresh Register

REG PLD Watch Dog Timer Load - 0xFFC80600
Bit 15
Field
RSVD
OPER R
RESET 0000
Field Description
Refresh
5.5.19

PLD Watchdog Control Register

The MVME2502 provides a watchdog control register.

Table 5-22 PLD Watchdog Control Register

REG PLD Watch Dog Timer Load - 0xFFC80604
Bit 15
Watchdog
Field
_EN
OPER R/W
RESET 0000
Field Description
EN Enable. If cleared, the watchdog timer is disabled. If set, the watchdog timer is
enabled.
112
14 13 12
RSVD RSVD RSVD
Counter Refresh. When the pattern 0x00DB is written, the watchdog counter
will be reset to zero.
14 13 12 11
RSV RSV RSV RSV
D D D D
R
11 10 9
RSVD RSVD RSVD
10 9 8 7 6
RSV RSV RSV RSV RSV
D D D D D
MVME2502 Installation and Use (6806800R96L)
Memory Maps and Registers
8 7 6 5 4 3 2 1 0
Refresh
RSVD
5 4 3 2 1
RSV RSV RSV RSV RSV
D D D D D
0
RSV
D