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SMART Embedded Computing Penguin Edge MVME250 Series Installation And User Manual

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Penguin Edge™ MVME2502
Installation and Use
P/N: 6806800R96L
July 2022

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Summary of Contents for SMART Embedded Computing Penguin Edge MVME250 Series

  • Page 1 Penguin Edge™ MVME2502 Installation and Use P/N: 6806800R96L July 2022...
  • Page 2 Legal Disclaimer* SMART Embedded Computing, Inc. (SMART EC), dba Penguin Solutions™, assumes no responsibility for errors or omissions in these materials. These materials are provided "AS IS" without warranty of any kind, either expressed or implied, including but not limited to, the implied warranties of merchantability, fitness for a particular purpose, or non- infringement.

  • Page 3: Table Of Contents

    Table of Contents About this Manual ............. . . 13 Safety Notes.
  • Page 4 Table of Contents 3.3.2 On-board LEDs ........... . 50 Connectors .
  • Page 5 Table of Contents Timers ..............81 4.4.1 Real Time Clock.
  • Page 6 Table of Contents Memory Map ............97 Flash Memory Map .
  • Page 7 Table of Contents 6.3.4 Booting from an SD Card ..........122 6.3.5 Booting VxWorks Through the Network .
  • Page 8 Table of Contents MVME2502 Installation and Use (6806800R96L)
  • Page 9 List of Figures Figure 1-1 Serial Number Location-ENP1 Variant ........30 Figure 1-2 Serial Number Location-ENP2 Variant .
  • Page 10 List of Figures MVME2502 Installation and Use (6806800R96L)
  • Page 11 List of Tables Table 1-1 Board Standard Compliances ......... . . 29 Table 1-2 Mechanical Data .
  • Page 12 List of Tables Table 5-6 PLD Month Register ..........101 Table 5-7 PLD Day Register .

  • Page 13: About This Manual

    About this Manual Overview of Contents This manual is intended for users who install and configure MVME2502 product. It is assumed that the user is familiar with the standard cabling procedures, configuration of operating systems, U-Boot system and MVME Chassis. The purpose of this manual is to describe MVME2502 product and the services it provides.
  • Page 14 About this Manual About this Manual Abbreviations This document uses the following abbreviations: Term Definition Common On-Chip Processor CPLD Complex Programmable Logic Device DDR3 Double Data Rate 3 DUART Dual Universal Asynchronous Receiver Transmitter EEPROM Erasable Programmable Read-Only Memory Federal Communications Commission FPGA Field Programmable Gate Array GPIO...
  • Page 15 About this Manual Term Definition UART Universal Asynchronous Receiver-Transmitter VITA VMEbus International Trade Association Versa Module Eurocard PCI Express Mezzanine Card Conventions The following table describes the conventions used throughout this manual. . Notation Description Typical notation for hexadecimal numbers (digits are 0 through F), for 0x00000000 example used for addresses and offsets Same for binary numbers (digits are 0 and 1)
  • Page 16 About this Manual About this Manual Notation Description Indicates a hazardous situation which, if not avoided, could result in death or serious injury Indicates a hazardous situation which, if not avoided, may result in minor or moderate injury Indicates a property damage message Indicates a hot surface that could result in moderate or serious injury Indicates an electrical situation that could result in moderate injury or death Indicates that when working in an ESD environment care should be taken...
  • Page 17 6806800R96H March 2020 3.4.1.3 (removed reference to J5 and MTG). Added table to Section 4.5 titled Ethernet Port Device Names. Re-branded to SMART Embedded Computing template. Updated Conventions table; updated 6806800R96G September 2019 Freescale to NXP; removed Ordering Information table; added Ordering and Support Information;...
  • Page 18 About this Manual About this Manual MVME2502 Installation and Use (6806800R96L)

  • Page 19: Safety Notes

    Safety Notes This section provides warnings that precede potentially dangerous procedures throughout this manual. Instructions contained in the warnings must be followed during all phases of operation, service, and repair of this equipment. You should also employ all other safety precautions necessary for the operation of the equipment in your operating environment.
  • Page 20 Safety Notes Safety Notes system to show compliance with the above mentioned requirements. A proper installation in a compliant system will maintain the required performance. Use only shielded cables when connecting peripherals to assure that appropriate radio frequency emissions compliance is maintained. Operation Product Damage High humidity and condensation on the board surface causes short circuits.
  • Page 21 Safety Notes Product Damage Inserting or removing modules with power applied may result in damage to module components. Before installing or removing additional devices or modules, read the documentation that came with the product. Cabling and Connectors Product Damage RJ-45 connectors on modules are either twisted-pair Ethernet (TPE) or E1/T1/J1 network interfaces.
  • Page 22 Safety Notes Safety Notes Data Loss If the battery has low or insufficient power the RTC is initialized. Exchange the battery before seven years of actual battery use have elapsed. PCB and Battery Holder Damage Removing the battery with a screw driver may damage the PCB or the battery holder. To prevent damage, do not use a screw driver to remove the battery from its holder.

  • Page 23: Sicherheitshinweise

    Sicherheitshinweise Dieses Kapitel enthält Hinweise, die potentiell gefährlichen Prozeduren innerhalb dieses Handbuchs vorrangestellt sind. Beachten Sie unbedingt in allen Phasen des Betriebs, der Wartung und der Reparatur des Systems die Anweisungen, die diesen Hinweisen enthalten sind. Sie sollten außerdem alle anderen Vorsichtsmaßnahmen treffen, die für den Betrieb des Produktes innerhalb Ihrer Betriebsumgebung notwendig sind.
  • Page 24 Sicherheitshinweise Sicherheitshinweise Das Produkt arbeitet im Hochfrequenzbereich und erzeugt Störstrahlung. Bei unsachgemäßem Einbau und anderem als in diesem Handbuch beschriebenen Betrieb können Störungen im Hochfrequenzbereich auftreten. Wird das Produkt in einem Wohngebiet betrieben, so kann dies mit grosser Wahrscheinlichkeit zu starken Störungen führen, welche dann auf Kosten des Produktanwenders beseitigt werden müssen.
  • Page 25 Sicherheitshinweise Installation Datenverlust Das Herunterfahren oder die Deinstallation eines Boards bevor das Betriebssystem oder andere auf dem Board laufende Software ordnungsmemäss beendet wurde, kann zu partiellem Datenverlust sowie zu Schäden am Filesystem führen. Stellen Sie sicher, dass sämtliche Software auf dem Board ordnungsgemäss beendet wurde, bevor Sie das Board herunterfahren oder das Board aus dem Chassis entfernen.
  • Page 26 Sicherheitshinweise Sicherheitshinweise Beschädigungen des Blades zur Folge haben. Verwenden Sie deshalb nur den Batterietyp, der auch bereits eingesetzt wurde und befolgen Sie die Installationsanleitung. Datenverlust Wenn Sie die Batterie austauschen, können die Zeiteinstellungen verloren gehen. Eine Backupversorgung verhindert den Datenverlust während des Austauschs. Wenn Sie die Batterie schnell austauschen, bleiben die Zeiteinstellungen möglicherweise erhalten.

  • Page 27: Introduction

    Chapter 1 Introduction Overview The MVME2502 is a VME form-factor single-board computer based on the NXP® QorIQ® P2020 dual core processor which features e500 cores delivering an excellent performance- to-power ratio.The board has wide range of I/O options and is designed for applications such as industrial control, semiconductor process equipment, radar, sonar and transportation signaling.
  • Page 28 Introduction Introduction The front panel I/O configuration consists of two RJ-45 10/100/1000BASE-T  Ethernet ports, PMC/XMC front panel I/O (optional) a USB 2.0 port, a Micro DB9 RS-232 serial console port, and a reset/abort switch. It also has an LED to signal board failure and another LED that can be configured in the LED register.

  • Page 29: Standard Compliances

    Introduction Standard Compliances The product is designed to meet the following standards: Table 1-1 Board Standard Compliances Standard Description EN 60950-1/A11:2009 IEC 60950-1:2005 2nd Edition Safety Requirements (legal) CAN/CSA C22.2 No 60950-1 FCC Part 15, Subpart B, Class A (non- residential) ICES-003, Class A (non-residential) EMC Directive 89/336/EEC...

  • Page 30: Ordering Information

    Introduction Introduction Ordering Information Refer to the data sheet for the MVME2502 for a complete list of available variants and accessories. Refer to Appendix B, Related Documentation or consult your local Penguin Solutions sales representative for the availability of other variants. For technical assistance, documentation, or to report product damage or shortages, contact your local Penguin Solutions sales representative or visit https://www.penguinsolutions.com/edge/support/.

  • Page 31: Figure 1-2 Serial Number Location-Enp2 Variant

    Introduction Figure 1-2 Serial Number Location-ENP2 Variant MVME2502 Installation and Use (6806800R96L)
  • Page 32 Introduction Introduction MVME2502 Installation and Use (6806800R96L)

  • Page 33: Hardware Preparation And Installation

    Chapter 2 Hardware Preparation and Installation Overview This chapter provides unpacking instructions, hardware preparation, installation procedures of the board. Installation instructions for the optional PMC/XMC modules and transitions modules are also included. A fully implemented MVME2502 consists of the base board and the following modules: PCI Mezzanine Card (PMC) or PCI-E Mezzanine Card (XMC) for added versatility ...

  • Page 34: Unpacking And Inspecting The Board

    Hardware Preparation and Installation Hardware Preparation and Installation Unpacking and Inspecting the Board Read all notices and cautions prior to unpacking the product. NOTICE Damage of Circuits Electrostatic discharge and incorrect installation and removal can damage circuits or shorten its life. Before touching the board or electronic components, make sure that you are working in an ESD-safe environment.

  • Page 35: Environmental Requirements

    Hardware Preparation and Installation 2.3.1 Environmental Requirements Operating temperatures refer to the temperature of the air circulating around the board and not to the component temperature. Table 2-1 Environmental Requirements Characteristics Commercial Versions Extended Temperature Versions MVME2502-02100202E MVME2502-02120201E Applicable Variants MVME2502-02100202S MVME2502-02120201S MVME2502-021CCxxxx...

  • Page 36: Power Requirements

    Hardware Preparation and Installation Hardware Preparation and Installation 2.3.2 Power Requirements The board uses +5.0V from the VMEbus backplane. On-board power supply generates required voltages for various ICs. The MVME2502 connects the +12V and -12V supplies from the backplane to the PMC sites, while the +3.3V power supplied to the PMC sites comes from the +5.0V backplane power.

  • Page 37: Equipment Requirements

    Hardware Preparation and Installation 2.3.3 Equipment Requirements The following are recommended to complete a MVME2502 system: VMEbus system enclosure  System console terminal  Operating system (and/or application software)  Transition module and connecting cables  Configuring the Board The board provides software control over most options. Settings can be modified to fit the user's specifications.

  • Page 38: Installing Accessories

    Hardware Preparation and Installation Hardware Preparation and Installation Installing Accessories 2.5.1 Rear Transition Module The MVME2502 does not support hot swap. Remove power to the rear slot or the system before installing the module. A PCMI/O Module (PIM) needs to be manually configured and installed before placing the transition module.

  • Page 39: Pmc/Xmc Support

    Hardware Preparation and Installation 9. Connect the cables to the transition module. Removal Procedure 1. Turn off the power. 2. Disconnect all the cables. 3. Press the red locking tabs (IEEE handles only) to eject the board. 4. Loosen and remove the screws adjacent to the injector/ejector levers that securing the module to the chassis.

  • Page 40: Installation Of Mvme2502-Hdmntkit1/Mvme2502-Hdmntkit2

    Hardware Preparation and Installation Hardware Preparation and Installation 4. Align the mating connectors properly and apply minimal pressure to the PMC/XMC until it is seated to the board. 5. Insert the four PMC/XMC mounting screws through the mounting holes on the bottom side of the board, and then thread the four mount points on the PMC/XMC.
  • Page 41 Hardware Preparation and Installation 2. Assemble the SATA adapter board to the blade and ensure that it is properly aligned with the standoff. Attach the screws to anchor the SATA adapter board to the blade. NOTE: The 3.3V key must be removed to install the SATA kit. 3.
  • Page 42 Hardware Preparation and Installation Hardware Preparation and Installation 4. Attach HDD with interface PCB to main board using screws as shown below: MVME2502 Installation and Use (6806800R96L)

  • Page 43: Installing And Removing The Board

    Hardware Preparation and Installation Installing and Removing the Board This section describes the recommended procedure for installing the board in a chassis. Read all warnings and instructions before installing the board. The MVME2502 does not support hot swap. Power off the slot or system and make sure that the serial ports and switches are properly configured.

  • Page 44: Completing The Installation

    Hardware Preparation and Installation Hardware Preparation and Installation 5. Move the injector/ejector levers in outward direction. 6. Hold top and bottom edges of the board and exert minimal force when pulling the board from the chassis to prevent pin damage. 7.

  • Page 45: Controls, Leds, And Connectors

    Chapter 3 Controls, LEDs, and Connectors Board Layout The following figure shows the components and connectors on the MVME2502 board. Figure 3-1 Board Layout ENP1 Variant MVME2502 Installation and Use (6806800R96L)

  • Page 46: Figure 3-2 Board Layout Enp2 Variant

    Controls, LEDs, and Connectors Controls, LEDs, and Connectors Figure 3-2 Board Layout ENP2 Variant MVME2502 Installation and Use (6806800R96L)

  • Page 47: Front Panel

    Controls, LEDs, and Connectors Front Panel The following components are found on the MVME2502 ENP1 and ENP2 front panel. Figure 3-3 Front Panel LEDs, Connectors and Switches PMC/XMC 2 PMC/XMC 1 USER 1 RESET SERIAL SWITCH PORT FAIL SPEED eTSEC 1 SPEED eTSEC 2 MVME2502 Installation and Use (6806800R96L)

  • Page 48: Reset Switch

    Controls, LEDs, and Connectors Controls, LEDs, and Connectors 3.2.1 Reset Switch The MVME2502 has a single push button switch that has both the abort and the reset functions. Pressing the switch for less than three seconds generates an abort interrupt if there is firmware that will read the GPIO2 (0xffdf0095) interrupt register.
  • Page 49 Controls, LEDs, and Connectors Table 3-1 Front Panel LEDs (continued) Label Function Location Color Description Normal operation after successful firmware boot. One or more on-board power rails has failed and the board has shutdown to protect the hardware. FAIL Board Fail Front panel Normal during power up, during hardware reset (such as a front...

  • Page 50: On-Board Leds

    Controls, LEDs, and Connectors Controls, LEDs, and Connectors 3.3.2 On-board LEDs The on-board LEDs are listed below. The LEDs are located on the rear side of the board just opposite of the battery location. To view the board, see 3.1 on page Figure 3-5 On-board LEDs Table 3-2 On-board LEDs Status...

  • Page 51: Connectors

    Controls, LEDs, and Connectors Connectors This section describes the pin assignments and signals for the connectors on the MVME2502 board. 3.4.1 Front Panel Connectors The following connectors are found on the outside of the MVME2502 board. These connectors are divided between the front panel connectors and the backplane connectors. The front panel connectors include the J1 and the J5 connectors.

  • Page 52: Front Panel Serial Port (Com1)

    Controls, LEDs, and Connectors Controls, LEDs, and Connectors 3.4.1.2 Front Panel Serial Port (COM1) There is one front access asynchronous serial port interface labeled COM1 that is routed to the micro mini DB-9 front panel connector. A male-to-male micro-mini DB9 adapter cable is available under Penguin Edge part number SERIAL-MINI-D (30-W2400E01A).

  • Page 53: Vmebus P1 Connector

    Controls, LEDs, and Connectors 3.4.1.4 VMEBus P1 Connector The VME P1 connector is a 160-pin DIN. The P1 connector provides power and VME signals for 24-bit address and 16-bit data. The pin assignments for the P1 connector is as follows: Table 3-6 VMEbus P1 Connector Row A...

  • Page 54: Vmebus P2 Connector

    Controls, LEDs, and Connectors Controls, LEDs, and Connectors Table 3-6 VMEbus P1 Connector (continued) Row A Row B Row C Row D Row Z IACKOUT ADD 30 +3.3V (not used) AM 4 ADD 31 ADD 7 IRQ7 ADD 32 +3.3V (not used) ADD 6 IRQ6 ADD 33...
  • Page 55 Controls, LEDs, and Connectors Table 3-7 VMEbus P2 Connector (continued) Row A Row B Row C Row D Row Z PMC IO 16 ADDRESS 28 PMC IO 15 GE3_2 - PMC IO 18 ADDRESS 29 PMC IO 17 Serial 2 RX PMC IO 20 ADDRESS 30 PMC IO 19...

  • Page 56: On-Board Connectors

    Controls, LEDs, and Connectors Controls, LEDs, and Connectors Table 3-7 VMEbus P2 Connector (continued) Row A Row B Row C Row D Row Z PMC IO 62 PMC IO 61 Serial 4 RTS PMC IO 64 PMC IO 63 3.4.2 On-board Connectors 3.4.2.1 SATA Connector (J3)

  • Page 57: Pmc Connectors

    Controls, LEDs, and Connectors Table 3-8 Custom SATA Connector (J3) (continued) Signal Description Signal Description +3.3V +3.3V 3.4.2.2 PMC Connectors The MVME2502 supports two PMC sites. It utilizes J14 to support PMC I/O that goes to the RTM PMC. The tables below show the pin out detail of J11/J111, J12/J222, J13/J333 and J14.
  • Page 58 Controls, LEDs, and Connectors Controls, LEDs, and Connectors Table 3-9 PMC J11/J111 Connector (continued) Signal Description Signal Description AD 15 AD 12 GNT A AD 11 REQ A AD 9 +3.3V AD 31 CBE0 AD 28 AD 6 AD 27 AD 5 AD 25 AD 4...

  • Page 59: Table 3-10 Pmc J12/J222 Connector

    Controls, LEDs, and Connectors Table 3-10 PMC J12/J222 Connector Signal Description Signal Description +12V JTAG TRST IDSELB JTAG TMS TRDY JTAG TDO +3.3V JTAG TDI STOP PERR +3.3V SERR BUSMODE2 (Pulled UP) CBE1 +3.3V PCI RESET AD 14 BUSMODE3 (PULLED DWN) AD 13 +3.3V M66EN...

  • Page 60: Table 3-11 Pmc J13/J333 Connector

    Controls, LEDs, and Connectors Controls, LEDs, and Connectors Table 3-10 PMC J12/J222 Connector (continued) Signal Description Signal Description +3.3V IDSEL AD 23 EREADY +3.3V AD 28 RSTOUT AD 18 ACK64 +3.3V AD 16 CBE2 Table 3-11 PMC J13/J333 Connector Signal Description Signal Description AD48 AD 47...

  • Page 61: Table 3-12 Pmc J14 Connector

    Controls, LEDs, and Connectors Table 3-11 PMC J13/J333 Connector (continued) Signal Description Signal Description AD 61 AD 40 AD 39 AD 60 AD 38 AD 59 AD 37 AD 58 AD 57 AD 36 +3.3V AD 35 AD 56 AD 34 AD 55 AD 33 AD 54...
  • Page 62 Controls, LEDs, and Connectors Controls, LEDs, and Connectors Table 3-12 PMC J14 Connector (continued) Signal Description Signal Description PMC IO 2 PMC IO 34 PMC IO 3 PMC IO 35 PMC IO 4 PMC IO 36 PMC IO 5 PMC IO 37 PMC IO 6 PMC IO 38 PMC IO 7...

  • Page 63: Jtag Connector (P6)

    Controls, LEDs, and Connectors Table 3-12 PMC J14 Connector (continued) Signal Description Signal Description PMC IO 26 PMC IO 58 PMC IO 27 PMC IO 59 PMC IO 28 PMC IO 60 PMC IO 29 PMC IO 61 PMC IO 30 PMC IO 62 PMC IO 31 PMC IO 63...

  • Page 64: Cop Connector P50(15)

    Controls, LEDs, and Connectors Controls, LEDs, and Connectors Table 3-13 JTAG Connector (P6) (continued) Signal Description Signal Description SCAN 2 TCK +3.3V FROM +5V SCAN 2 TDI SCAN 3 TMS SCAN 3 TCK1 SCAN 3 TDO SCAN 3 TCK 2 +2.5V SCAN 3 TCK 3 SCAN 3 TDI...

  • Page 65: Xmc Connector (Xj1)

    Controls, LEDs, and Connectors Table 3-14 COP Header (P50) (continued) Signal Description COP QACK JTAG TDI COP TRST COP RUNSTOP (Pulled UP) COP VDD SENSE JTAG TCK COP CHECK STOP IN JTAG TMS P2020 SW RESET COP PRESENT COP HARD RESET KEYING COP CHECK STOP OUT 3.4.2.5...
  • Page 66 Controls, LEDs, and Connectors Controls, LEDs, and Connectors Table 3-15 XMC Connector (XJ1) Pin out (continued) Row A Row B Row C Row D Row E Row F +3.3V +3.3V JTAG TMS +12V +3.3V +3.3V JTAG TMS -12V +3.3V JTAG TDO GA 0 BIST (PULLED TX0 -...

  • Page 67: Xmc Connector (Xj2)

    Controls, LEDs, and Connectors 3.4.2.6 XMC Connector (XJ2) Table 3-16 XMC Connector (XJ2) Pin out Row A Row B Row C Row D Row E Row F RX0 + RX0 - +3.3V RX1+ RX1- +3.3V JTAG TRST HRESET +3.3V +3.3V MRSTO JTAG TCK (PULLED UP)

  • Page 68: Switches

    Controls, LEDs, and Connectors Controls, LEDs, and Connectors Table 3-17 P2020 Debug Header (P4) Signal Description MSRCDI0 MSRCDI1 MDVAL MSRCDI2 TRIG_OUT MSRCDI3 TRIG_IN MSRCID4 Switches These switches control the configuration of the MVME2502. NOTICE Board Malfunction Switches marked as “reserved” might carry production-related functions and can cause the board to malfunction if their settings are changed.

  • Page 69: Figure 3-6 Geographical Address Switch

    Controls, LEDs, and Connectors Note that this switch is wired in parallel with the geographical address pins on the five row connector. These switches must be in the OFF position when installed in a five row chassis in order to get the correct address from the P1 connector. This switch also includes the SCON control switches.

  • Page 70: Smt Configuration Switch (S2)

    Controls, LEDs, and Connectors Controls, LEDs, and Connectors 3.5.2 SMT Configuration Switch (S2) This eight position SMT configuration switch controls the flash bank user defined switch, selects the flash boot image, and controls the safe start ENV settings. The default setting on all switch positions is OFF and is indicated by brackets in Table 3-1.
  • Page 71 Controls, LEDs, and Connectors Table 3-19 SMT Configuration Switch Settings (continued) SW2 DEFAULT Signal Name Description Notes This option can only be used if the PMC supports PCI-X interface. The board will automatically detect the frequency of operation of PCI frequency OFF (133 MHz) PMC_133 the PMC and the board will...
  • Page 72 Controls, LEDs, and Connectors Controls, LEDs, and Connectors MVME2502 Installation and Use (6806800R96L)

  • Page 73: Functional Description

    Chapter 4 Functional Description Block Diagram The MVME2502 block diagram is illustrated in 4-1. All variants provide front panel Figure access to one serial port via a micro-mini DB-9 connector, two 10/100/1000 Ethernet port (one is configurable to be routed to the front panel or the rear panel) through a RJ-45 connector and one Type A USB Port.

  • Page 74: Chipset

    Functional Description Functional Description Chipset The MVME2502 utilizes the QorIQ P20x0 integrated processor. It offers an excellent combination of protocol and interface support which includes the following components. QorIQ P2020 integrated processor or e500 processor core  PCI Express interface ...

  • Page 75: Pci Express Interface

    Functional Description Up to four physical banks; each bank can be independently addressed to 64 Mbit  to 4Gbit memory devices (depending on the internal device configuration with x8/x16/x32 data ports). Chipset interleaving and partial array self-refresh  Data mask signal and read-modify-write for sub-double-word writes when ECC is ...

  • Page 76: Usb Interface

    Functional Description Functional Description 4.2.7 USB Interface The P2020 implements a USB 2.0 compliant serial interface engine. For more information, USB on page 4.2.8 DUART The chipset provides two universal asynchronous receiver/transmitter (UART). Each UART is clocked by the CCB clock and is compatible with PC16522D. As a full-duplex interface, it provides 16-byte FIFO for both transmitter and receiver mode.

  • Page 77: Security Engine (Sec) 3.1

    Functional Description Table 4-1 P2020 GPIO Functions (continued) GPIO bit CPU Pin # Function Not connected Not connected Not connected Not connected Connected to pin T6 of the CPLD (unused input) Connected to pin R6 of the CPLD (unused input) Connected to INTA of the QUART.

  • Page 78: Common On-Chip Processor (Cop)

    Functional Description Functional Description 4.2.13 Common On-Chip Processor (COP) The COP is the debug interface of the QorIQ P2020 Processor. It allows a remote computer system to access and control the internal operation of the processor. The COP interface connects primarily through the JTAG and has additional status monitoring signals. The COP has additional features like breakpoints, watch points, register and memory examination/modification and other standard debugging features.
  • Page 79 Functional Description Table 4-2 P2020 Strapping Options (continued) Reset Config Functional Signal Default Configuration Resistor Description Name Value Name Options DDR SDRAM controller debug info DMA2_DACK0 cfg_mem_debug driven to MSRCID/MDVAL (default) Debug information is not driven on DMA2_DDONE0 cfg_ddr_debug ECC pins (default) eTSEC1 and eTSEC2 Ethernet EC_MDC cfg_tsec_reduce...
  • Page 80 Functional Description Functional Description Table 4-2 P2020 Strapping Options (continued) Reset Config Functional Signal Default Configuration Resistor Description Name Value Name Options eTSEC, ethernet management, 1588 LVDD_VSEL interfaces = 2.5V Local bus and GPIO[8:15] interfaces BVD_VSEL[0:1] = 3.3V CVDD_VSEL[0:1] USB, eSDHC, SPI interface = 3.3V LA[20:22] UART_SOUT[0] TRIG_OUT...

  • Page 81: System Memory

    Functional Description System Memory The P2020 integrated memory controller supports both DDR2 and DDR3 memory devices. It has one channel and can be configured up to four memory banks with x8, x16 and x32 devices. Selection of 4GB devices allows support up to 16GB of memory. ECC is also supported.

  • Page 82: Ethernet Interfaces

    Functional Description Functional Description Ethernet Interfaces The MVME2502 has three eTSEC controllers. Each one supports RGMII, GMII, and SGMII interface to the external PHY. All controllers can only be utilized when using the RGMII interface. Using the GMII allows only up to two usable controllers. MVME2502 provides two 10/100/1000 Ethernet interfaces on the front panel and another two are routed to the RTM through the backplane connector.

  • Page 83: Spi Flash Memory

    Functional Description 4.6.1 SPI Flash Memory The MVME2502 has two 8 MB on-board serial flash. Both contain the ENV variables and the U-Boot firmware image, which is about 513 KB in size. Both SPI flash contain the same programming for firmware redundancy and crisis recovery. The SPI flash is programmed through the JTAG interface or through an on-board SPI flash programming header.

  • Page 84: Crisis Recovery

    Functional Description Functional Description The MVME2502 CPLD controls the chip select to SPI devices A and B. The CPLD chip select control is based on the Switch Bank (S2-2). Figure 4-2 SPI Device Multiplexing Logic On power-up, the selection of the SPI boot device is strictly based upon the Switch Bank (S2-2) setting.

  • Page 85: Front Uart Control

    Functional Description Crisis recovery is performed as follows: 1. Power off the board. 2. Set Switch S2-2 to ON to point to SPI Device B (crisis image). 3. Power on the board. 4. Press <h> key on the keyboard to go to the U-Boot prompt. 5.

  • Page 86: Pmc/Xmc Sites

    Functional Description Functional Description PMC/XMC Sites The MVME2502 hosts two PMC/XMC sites and accepts either a PMC or an XMC add-on card. Only an XMC or a PMC may be populated at any given time as both occupy the same physical space on the PCB.

  • Page 87: Pmc Add-On Card

    Functional Description 4.9.1 PMC Add-on Card The MVME2502 PMC interface utilizes IDT’s TSI384 as the PCIe/PCI-X bridge. It supports up to 8.5Gbps (64 bits x 133MHz). The on-board switch S2-5 configures the Tsi384 to run on either 100MHz or 133MHz, with 133MHz as default. The MVME2502 supports multi-function PMCs and processor PMCs (PrPMCs).

  • Page 88: Tsi148 Vme Controller

    Functional Description Functional Description 4.11.1 Tsi148 VME Controller The VMEbus interface for the MVME2502 is provided by the Tsi148 VMEbus controller. The Tsi148 provides the required VME, VME extensions, and 2eSST functions. TI SN74VMEH22501transceivers are used to buffer the VME signals between the Tsi148 and the VME backplane.

  • Page 89: Reset/Control Cpld

    Functional Description Following are the I C bus addresses: Table 4-4 P2020 I C Port1 Devices C 8-bit Base Ref Designator I C Device Device Type Address Temperature Sensor ADT 7461 Temperature Sensor AT24C02 (256x8) VPD EEPROM AT24C64 (8192x8) Reserved for RTM User EEPROM 1 AT24C512 (65536x8) User EEPROM 2...

  • Page 90: Power Management

    Functional Description Functional Description 4.15 Power Management The MVME2502 backplane is utilized to derive +3.3V, +2.5V, +1.8V, +1.5V, +1.2V, +1.05V voltage rail. Each voltage rail is controlled by the CPLD through an enable pin of the regulator, while the output is monitored through power good signal. If a voltage rail fails, the CPLD will disable all of the regulators.

  • Page 91: Clock Structure

    Functional Description 4.16 Clock Structure A total of three IDT chips, a discrete oscillator and crystal to support all the clock requirements of MVME2502. Figure 4-3 Clock Distribution Diagram MVME2502 Installation and Use (6806800R96L)

  • Page 92: Reset Structure

    Functional Description Functional Description 4.17 Reset Structure The MVME2502 reset will initiate after the power up sequence if the 1.5 V power supply is GOOD. When the board is at READY state, the reset logic will monitor the reset sources and implement the necessary reset function.

  • Page 93: Debugging Support

    Functional Description 4.20 Debugging Support The following information shows the details of Penguin Edge debugging support as applied to the MVME2502. 4.20.1 POST Code Indicator The following table shows the LED status of the POST Codes. For the location of the POST Code LEDs, see On-board LEDs on page Logic 1 means LED is ON, Logic 2 means LED is OFF.

  • Page 94: Custom Debugging

    Functional Description Functional Description The JTAG board provides three different connectors for the ASSET hardware, flash programming and the MVME2502 JTAG connector. The board is equipped with TTL buffers to help improve the signal quality as it traverses over the wires. Figure 4-4 JTAG Chain Diagram 4.20.3 Custom Debugging...

  • Page 95: Rear Transition Module (Rtm)

    Functional Description 4.21 Rear Transition Module (RTM) The MVME2502 RTM Block diagram is illustrated below: Figure 4-5 RTM Block Diagram The MVME2502 is compatible with the MVME7216E RTM. The MVME7216E RTM is for I/O routing through the rear of a compact VMEbus chassis. It connects directly to the VME backplane in chassis with an 80 mm deep rear transition area.
  • Page 96 Functional Description Functional Description MVME2502 Installation and Use (6806800R96L)

  • Page 97: Memory Maps And Registers

    Chapter 5 Memory Maps and Registers Overview The system resources including system control and status registers, external timers, and the QUART are mapped into 16MB address range accessible from the MVME2502 local bus through the P2020 QorIQ LBC. Memory Map The following table shows the physical address map of the MVME2502.

  • Page 98: Flash Memory Map

    Memory Maps and Registers Memory Maps and Registers Flash Memory Map The table below lists the memory range designated to U-boot and ENV variables. Table 5-2 Flash Memory Map Description Memory Area U-boot 0x00000000 0x0008ffff Reserved 0x00090000 0x0009ffff ENV Variables 0x00100000 0x0011ffff Available Flash 0x00120000 0x007fffff...

  • Page 99: Table 5-3 Linux Devices Memory Map

    Memory Maps and Registers Table 5-3 Linux Devices Memory Map (continued) Device Memory Range Memory Area Size CPLD 0xffdf0000 0xffdf0fff ecm local access window CCSR 0xffe00000 0xffe00ffff ecm (Error Correction Module) CCSR 0xffe01000 0xffe01fff Memory Controller CCSR 0xffe02000 0xffe02fff I2C1 CCSR 0xffe03000 0xffe030ff 256B I2C2 CCSR...

  • Page 100: Programmable Logic Device (Pld) Registers

    Memory Maps and Registers Memory Maps and Registers Table 5-3 Linux Devices Memory Map (continued) Device Memory Range Memory Area Size msi CCSR 0xffe41600 0xffe4167f 128B mpic CCSR 0xffe40000 0xffe7ffff 256KB Global Utilities CCSR 0xffee0000 0xffee0fff L2 Cache Mem 0xf0f80000 0xf0ffffff 512KB Programmable Logic Device (PLD) Registers 5.5.1...

  • Page 101: Pld Month Register

    Memory Maps and Registers Table 5-5 PLD Year Register PLD Year Register - 0xFFDF0004 Field PLD_REV OPER RESET 0x12 5.5.3 PLD Month Register The MVME2502 PLD provides an 8-bit register which contains the build month of the timers/registers PLD. Table 5-6 PLD Month Register PLD Year Register - 0xFFDF0005 Field...

  • Page 102: Pld Sequence Register

    Memory Maps and Registers Memory Maps and Registers 5.5.5 PLD Sequence Register The MVME2502 PLD provides an 8-bit register which contains the sequence of the PLD which is in synchrony with the PCB version. Table 5-8 PLD Sequence Register PLD Revision Register - 0xFFDF0007 Field PLD_REV OPER...

  • Page 103: Pld Led Control Register

    Memory Maps and Registers PWR_V1P2_SW_PWRGD 1.2V SW Supply power good indicator PWR_V1P5_PWRGD 1.5V Supply power good indicator 1 - Supply Good and Stable 0 - Otherwise 5.5.7 PLD LED Control Register The MVME2502 PLD provides an 8-bit register which controls the eight LEDs. Table 5-10 PLD LED Control Register PLD LED_CTRL - 0xFFDF001C Field...

  • Page 104: Pld Pci/Pmc/Xmc (Slot2) Monitor Register

    Memory Maps and Registers Memory Maps and Registers Field Description MUX1_SEL_SW Select for PCIe MUX1 (R/W) 1 - PMC 0 - XMC SW2-4 SW2-4 state (User defined) 0 - SW2-4 closed 1 - SW2-4 open (default) PMC1_EREADY Indicates PCI device is ready for enumeration 1 - PMC ready for enumeration 0 - PMC is not ready for enumeration PMC1P_N...

  • Page 105: Pld U-Boot And Tsi Monitor Register

    Memory Maps and Registers Field Description SD1_MUX_SEL[1:0] Select for PCIe MUX1 (Read Only) 11 - XMC (default) 10 - PMC 01-SATA 00-Unused SW2-4 SW2-4 state (User defined) 0 - SW2-4 closed 1 - SW2-4 open (default) PMC2_EREADY Indicates PCI device is ready for enumeration 1 - PMC ready for enumeration 0 - PMC is not ready for enumeration SATA0_DETECT_N...

  • Page 106: Pld Boot Bank Register

    Memory Maps and Registers Memory Maps and Registers Field Description BDFAIL_N TSI148 BDFAIL_N Pin out 1 - No TSI Fail 0 - TSI Fail NORMAL_ENV Normal Environment Switch Indicator 1 - Use safe ENV 0 - Use normal ENV SCON System Controller Indicator 1 - System Controller 0 - Non-system Controller...

  • Page 107: Pld Write Protect And I C Debug Register

    Memory Maps and Registers 5.5.12 PLD Write Protect and I C Debug Register The MVME2502 PLD provides an 8-bit register which is used to indicate the status of I and SPI write-protect manual switches and is used to control the SPI write-enable. The I debug ports are also provided in this register which is used in controlling the bus’...

  • Page 108: Pld Test Register 1

    Memory Maps and Registers Memory Maps and Registers When SERIAL_FLASH_WP is set to LOW, this port will automatically read as low due to AND connection between the two ports. 5.5.13 PLD Test Register 1 The MVME2502 PLD provides an 8-bit general purpose read/write register which is used by the software for PLD testing or general status bit storage.

  • Page 109: Pld Test Register 2

    Memory Maps and Registers 5.5.14 PLD Test Register 2 The MVME2502 PLD provides an 8-bit general purpose read/write register which is used by the software for PLD testing or general status bit storage. Table 5-17 PLD Test Register 2 PLD Write Protect I2C Debug- 0xFFDF0095 Field TEST_REG1 OPER...

  • Page 110: Pld Shutdown And Reset Control And Reset Reason Register

    Memory Maps and Registers Memory Maps and Registers Abort switch interrupt if pressed less than three seconds. 1 - Interrupt enabled 0 - No Interrupt TICK0_INT Tick Timer 0 interrupt 1 - Interrupt enabled 0 - No Interrupt TICK1_INT Tick Timer 1 interrupt 1 - Interrupt enabled 0 - No Interrupt TICK2_INT...

  • Page 111: Emmc Reset Register

    Memory Maps and Registers Clear_Cause Clear Reset Reason (self clearing) 1 - Clear Reason 0 - None CPU_RESET CPU_HRESET_REQ_L Reset Reason 1 - Reset is due to CPU_HRESET_REQ_L signal 0 -None WD_TIMEOUT Watchdog Timeout Reset Reason 1 - Reset is due to watchdog timing out 0 - None LRSTO TSI LRSTO Reset Reason...

  • Page 112: Pld Watchdog Timer Refresh Register

    Memory Maps and Registers Memory Maps and Registers 5.5.18 PLD Watchdog Timer Refresh Register The MVME2502 provides a watchdog timer refresh register. Table 5-21 PLD Watchdog Timer Refresh Register PLD Watch Dog Timer Load - 0xFFC80600 7 6 5 4 3 2 1 0 Field Refresh RSVD...

  • Page 113: Pld Watchdog Timer Count Register

    Memory Maps and Registers 5.5.20 PLD Watchdog Timer Count Register The MVME2502 provides a watchdog timer count register. Table 5-23 PLD Watchdog Timer Count Register PLD Watchdog Timer Count - 0xffc80606 15:0 Field Count OPER RESET 0xEA60 (60secs) Field Description Count Count.

  • Page 114: External Timer Registers

    Memory Maps and Registers Memory Maps and Registers External Timer Registers The MVME2502 provides a set of tick timer registers to access the three external timers implemented in the timers/registers PLD. These registers are 32-bit and are word writable. The following sections describe the timer prescaler and control register: 5.6.1 Prescaler Register The prescaler adjust value is determined by this formula:...

  • Page 115: Control Registers

    Memory Maps and Registers 5.6.2 Control Registers Table 5-26 Control Registers Tick Timer 0 Control Register - 0xFFC80202 Tick Timer 1 Control Register - 0xFFC80302 Tick Timer 2 Control Register - 0xFFC80402 Field RSVD INTS CINT ENINT OVF RSVD COVF COC ENC OPER RESET 0x0000 Field Description...

  • Page 116: Table 5-27 Compare High Word Registers

    Memory Maps and Registers Memory Maps and Registers When programming the tick timer for periodic interrupt, the counter should be cleared to zero by software and then enabled. If the counter does not initially start at zero, the time to the first interrupt may be longer or shorter than expected.

  • Page 117: Counter High And Low Word Registers

    Memory Maps and Registers 5.6.4 Counter High and Low Word Registers When enabled, the tick timer counter register increments every microsecond. Software may read or write the counter at any time. Table 5-29 Counter High Word Registers Tick Timer 0 Counter Value High Word - 0xFFC80208 Tick Timer 1 Counter Value High Word - 0xFFC80308 Tick Timer 2 Counter Value High Word - 0xFFC80408 Field...
  • Page 118 Memory Maps and Registers Memory Maps and Registers MVME2502 Installation and Use (6806800R96L)

  • Page 119: Boot System

    Chapter 6 Boot System Overview The U-boot address is relocated near to the end of DRAM. The address of U-boot is not fixed and it varies from release to release based on the type of changes done. It may also change based on the type of devices that the user has populated on the board.

  • Page 120: Boot Options

    Boot System Boot System These serial access parameters are the default values. These values can be changed within the U-Boot. For details, refer to the U-Boot documentation. 3. Boot the MVME2502. 4. When prompted, press the <h> key. U-Boot aborts the boot sequence and enters into a command line interface mode. Enter the command to disable the U-Boot auto- setenv bootdelay -1;...

  • Page 121: Booting From An Optional Sata Drive

    Boot System 6.3.2 Booting from an Optional SATA Drive 1. Make sure that the kernel, dtb, and ramdisk are saved in the SATA drive with ext2 partition. 2. Configure U-Boot environment variable: setenv File_uImage <kernel_image> setenv File_dtb <kernel dtb> setenv File_ramdisk <ramdisk> saveenv 3.

  • Page 122: Booting From An Sd Card

    Boot System Boot System 6.3.4 Booting from an SD Card 1. Make sure that the kernel, dtb, and ramdisk are saved in the SD card with FAT partition. 2. Configure the U-Boot environment variable: setenv File_uImage <kernel_image> setenv File_dtb <kernel dtb> setenv File_ramdisk <ramdisk>...

  • Page 123: Using The Persistent Memory Feature

    Boot System run vxboot Using the Persistent Memory Feature The persistent memory means that the RAM's memory is not deleted during a reset. Power cycling, or by temporarily removing the power and then powering up the blade again, will delete the memory content. The persistent memory feature is enabled by default. This feature is used in many situations, which includes: Analyzing kernel logs after a Linux kernel panic ...

  • Page 124: Mvme2502 Specific U-Boot Commands

    Boot System Boot System MVME2502 Specific U-Boot Commands Table 6-1 MVME2502 Specific U-Boot Commands Command Description Print or set address offset base Print board info structure bdinfo Boot default, i.e., run bootcmd boot Boot default, i.e., run bootcmd bootd Boot from an ELF image in memory bootelf Boot application image from memory bootm...
  • Page 125 Boot System Table 6-1 MVME2502 Specific U-Boot Commands (continued) Command Description Flattened device tree utility commands Start application at address addr Print online help help C sub-system Print header information for application image iminfo Extract a part of a multi-image imxtract Enable or disable interrupts interrupts...
  • Page 126 Boot System Boot System Table 6-1 MVME2502 Specific U-Boot Commands (continued) Command Description List and access PCI Configuration Space Show information about devices on PCI bus pci_info Send ICMP ECHO_REQUEST to network host ping Print environment variables printenv Boot image through network using RARP/TFTP protocol rarpboot Perform RESET of the CPU reset...

  • Page 127: Updating U-Boot

    Boot System Updating U-Boot To update the U-Boot, place the image in the RAM (address 0x1000000 in this example) before copying it to the SPI flash. The following procedure will replace the image in SPI bank 0: 1. Disable SPI write-protect in CPLD register PLD Write Protect and I C Debug Register on page...
  • Page 128 Boot System Boot System MVME2502 Installation and Use (6806800R96L)

  • Page 129: Programming Model

    Chapter 7 Programming Model Overview This chapter includes additional programming information for the MVME2502. Reset Configuration The MVME2502 supports the power-on reset (POR) pin sampling method for processor reset configuration. Each option and the corresponding default setting are described in the following table.
  • Page 130 Programming Model Programming Model Table 7-1 POR Configuration Settings (continued) CONFIG CONFIG PINS CONFIG SELECTION REMARKS CFG_BOOT_SEQ[1:0] Boot LGPL3/LFWP, = BOOT SEQUENCE Sequence LGPL5 DISABLED Debug information Memory from the DDR SDRAM Debug DMA2_DACK0 controller is driven on Config the MSPCID and MDVAL signs (default) Debug information is not driven on ECC...
  • Page 131 Programming Model Table 7-1 POR Configuration Settings (continued) CONFIG CONFIG PINS CONFIG SELECTION REMARKS LA[22:20] UART_SOUT[0], Engineering TRIG_OUT, 11111111 Default (for future use) MSRCID[1], MSRCID[4], DMA1_DDONE_B[0] SerDes expects 100 SerDes Ref TSEC_1588_ALAR MHz reference clock Clock Config M_OUT1 frequency (default). eTSEC2 Ethernet interface operates in ETSEC2...
  • Page 132 Programming Model Programming Model Table 7-1 POR Configuration Settings (continued) CONFIG CONFIG PINS CONFIG SELECTION REMARKS The eTSEC2 controller operates using the GMII protocol (or ETSEC2 TSEC2_TXD0, RGMII, if configured in Protocol TSEC2_TXD7 reduced mode) if its not configured to operate in SGMII mode.

  • Page 133: Interrupt Controller

    Programming Model Table 7-1 POR Configuration Settings (continued) CONFIG CONFIG PINS CONFIG SELECTION REMARKS System SYSCLOCK is above LA[28] Speed 66 MHz SDHC Card Detect TSEC2_TXD_5 Not Inverted Polarity RAPID Default RapidIO is not used System Size Interrupt Controller The MVME2502 uses the MPC8548E integrated programmable interrupt controller (PIC) to manage locally generated interrupts.

  • Page 134: I 2 C Bus Device Addressing

    Programming Model Programming Model Table 7-2 MVME2502 Interrupt List (continued) Interrupt Usage Interrupt Line Interface to CPU Description (Schematic) RTC (Real Time IRQ8/ GPIO1 DS1337 INT_A Clock) IRQ9/ GPIO2 CPLD Interrupt NMI and 3 Tick Timer Interrupts IRQ10// GPIO3 CPLD Interrupt Not used IRQ11// GPIO4 QUART_IRQ0...

  • Page 135: Ethernet Phy Address

    Programming Model Ethernet PHY Address The assigned Ethernet PHY on the MII management bus is shown in the following table. Table 7-4 PHY Types and MII Management Bus Address Ethernet PHY MIIM Function / Location PHY Types Port Address Gigabit Ethernet port routed to front panel or back TSEC1 BCM54616 panel, set by GBE_MUX_SEL in S2.

  • Page 136: Lbc Timing Parameters

    Programming Model Programming Model 7.6.4 LBC Timing Parameters The following table defines the timing parameters for the devices on the local bus. Table 7-5 LBC Timing Parameters MRAM UART 0 UART 1 UART 2 UART 3 CPLD Timers BCTLD CSNT XACS 0011 0011...

  • Page 137: Clock Distribution

    Programming Model EHTR Extended hold time on read accesses. 0 - The memory controller generates normal timing. No additional cycles are inserted External address latch delay 0 - No additional bus clock cycles (LALE asserted for one bus clock cycle only) Clock Distribution The clock function generates and distributes all the clocks required for system operation.

  • Page 138: System Clock

    Programming Model Programming Model Table 7-6 Clock Distribution (continued) Clock Tree Device Clock Signal Frequency Source TSI384 CLK_PCIEC3 100MHz ICS9FG111 DIFF CLK_88SE9125_PCIE_100 88SE9125 100MHz ICS9FG112 DIFF CPLD CLK_CPLD 1.8432MHz Oscillator +3.3V CLK_USB_1_24MHZ 24MHz Oscillator +3.3V QorIQ P2020 CPU_RTC 1MHz CPLD +3.3V 33/66/100/133 CLK_PMC1...

  • Page 139: Local Bus Controller Clock Divisor

    Programming Model 7.7.3 Local Bus Controller Clock Divisor The local bus controller (LBC) clock output is connected to the CPLD for LBC bus transaction. It is also the source of 1 MHz (CPU_RTC) and CPLD tick timers. MVME2502 Installation and Use (6806800R96L)
  • Page 140 Programming Model Programming Model MVME2502 Installation and Use (6806800R96L)

  • Page 141: Replacing The Battery

    Appendix A Replacing the Battery Replacing the Battery The figure below shows the location of the board battery. Figure A-1 Battery Location ENP1 Variant MVME2502 Installation and Use (6806800R96L)

  • Page 142: Figure A-2 Battery Location Enp2 Variant

    Replacing the Battery Replacing the Battery Figure A-2 Battery Location ENP2 Variant MVME2502 Installation and Use (6806800R96L)
  • Page 143 Replacing the Battery The battery provides seven years of data retention, summing up all periods of actual data use. Penguin Solutions therefore assumes that there is usually no need to replace the battery except, for example, in case of long-term spare part handling. NOTICE Board/System Damage Incorrect replacement of lithium batteries can result in a hazardous explosion.
  • Page 144 Replacing the Battery Replacing the Battery MVME2502 Installation and Use (6806800R96L)

  • Page 145: Related Documentation

    Appendix B Related Documentation Penguin Solutions Documentation Technical documentation can be found by using the Documentation Search at or you can obtain electronic copies of https://www.penguinsolutions.com/edge/support/ documentation by contacting your local sales representative. Table B-1 Penguin Edge Documentation Document Title Document Number MVME2502 Data Sheet MVME2502-DS...

  • Page 146: Related Specifications

    Related Documentation Related Documentation Related Specifications For additional information, refer to the following table for related specifications. As an additional help, a source for the listed document is provided. Please note that, while these sources have been verified, the information is subject to change without notice. Table B-3 Related Specifications Organization...
  • Page 147 Related Documentation Table B-3 Related Specifications (continued) Organization Document Serial ATA Serial ATA (SATA) Specification Revision 2.6 International Organization Serial ATA II: Extensions to Serial ATA 1.0 Revision 1.0 (SATA-IO) Trusted Computing TPM Specification 1.2, Level 2 Revision 103 Version 1.2 Group (TCG) USB Implementers Universal Serial Bus Specification (USB) Revision 2.0...
  • Page 148 Related Documentation Related Documentation MVME2502 Installation and Use (6806800R96L)
  • Page 150 Penguin Solutions is a trade name used by SMART Embedded Computing, Inc., a wholly owned subsidiary of SMART Global Holdings, Inc. Penguin Edge is a trademark owned by Penguin Computing, Inc., a wholly owned subsidiary of SMART Global Holdings, Inc. NXP and QorIQ are trademarks of...

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