System Clock; Real Time Clock Input; Local Bus Controller Clock Divisor - SMART Embedded Computing MVME2502 Installation And Use Manual

Programming Model
Table 7-6
Device
88SE9125
CPLD
USB
QorIQ P2020
PMC
TSI148
RTC
CPLD
QUART
ICS83905
7.7.1

System Clock

The system and DDR clock is driven by ICS840S07I device. The following table defines the
clock frequency.
Table 7-7
SYSCLK
100MHz
7.7.2

Real Time Clock Input

The RTC clock input is driven by 1 MHz clock generated by the CPLD. This provides a fixed
clock reference for the QorIQ P2020 PIC timers which the software can use as a known
time reference.
7.7.3

Local Bus Controller Clock Divisor

The local bus controller (LBC) clock output is connected to the CPLD for LBC bus
transaction. It is also the source of 1 MHz (CPU_RTC) and CPLD tick timers.
134
Clock Distribution (continued)
Clock Signal
CLK_88SE9125_PCIE_100
MHZ
CLK_CPLD
CLK_USB_1_24MHZ
CPU_RTC
CLK_PMC1
CLK_PCI_BR3
CLK_32K
CPU_LCK0
CLK_QUART
CLK_25MHZ_ICS9FG108
System Clock
CORE
800/1200MHz
Frequency
100MHz
1.8432MHz
24MHz
1MHz
33/66/100/133
MHz
133MHz
32.768KHz
25MHz
1.8432MHz
25MHz
CCB Clock (Platform)
400MHz
MVME2502 Installation and Use (6806800R96G)
Programming Model
Clock Tree
VIO
Source
ICS9FG112 DIFF
Oscillator +3.3V
Oscillator +3.3V
CPLD +3.3V
TSI384 +3.3V
ICS840S07I +3.3V
DS32KHz +3.3V
QorIQ P2020 +3.3V
CPLD +3.3V
ICS83905AGILF +3.3V
DDR3 LBC
400MHz 25MHz