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1 - LED on
0 - LED off
For more information on LEDs, refer to
5.5.8
PLD PCI/PMC/XMC (Slot1) Monitor Register
The MVME2502 PLD provides an 8-bit register which indicates the status of the
PCI/PMC/XMC interface signals.
Table 5-11
REG
Bit
Field
OPER
RESET
Field Description
MUX1_SEL_SW
SW2-4
PMC1_EREADY
PMC1P_N
XMCP1_N
PCI1_PCIXCAP
MVME2502 Installation and Use (6806800R96G)
PLD PCI/PMC/XMC (Slot1) Monitor Register
PLD PCI_PMC_XMC_MNTR - 0xFFDF001D
7
6
5
MUX1_S
RSVD
RSVD
EL_SW
R
0
0
1
Select for PCIe MUX1 (R/W)
1 - PMC
0 - XMC
SW2-4 state (User defined)
0 - SW2-4 closed
1 - SW2-4 open (default)
Indicates PCI device is ready for enumeration
1 - PMC ready for enumeration
0 - PMC is not ready for enumeration
PMC Presence Indicator
1 - PMC is not present
0 - PMC is present
XMC Presence Indicator
1 - XMC is not present
0 - XMC is present
PCI Capability Indicator
1 - PCI-X capable
0 - PCI capable
Memory Maps and Registers
Table 3-1
and
Table
3-2.
4
3
2
PMC1_E
PMC1P_
SW2-4
READY
N
X
X
X
1
0
XMCP1_
PCI1_PC
N
IXCAP
X
X
101
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