Common On-Chip Processor (Cop); P2020 Strapping Pins; Table 4-2 P2020 Strapping Options - SMART Embedded Computing MVME2502 Installation And Use Manual

Functional Description
4.2.13

Common On-Chip Processor (COP)

The COP is the debug interface of the QorIQ P2020 Processor. It allows a remote computer
system to access and control the internal operation of the processor. The COP interface
connects primarily through the JTAG and has additional status monitoring signals. The
COP has additional features like breakpoints, watch points, register and memory
examination/modification and other standard debugging features.
4.2.14

P2020 Strapping Pins

The following table lists all the P2020 strapping pins and the default configuration settings
for the MVME2502.
Table 4-2
Functional Signal
Name
LA[29:31]
TSEC_1588_CLKOUT
TSEC_1588_PULSE_
OUT1
TSEC_1588_PULSE_
OUT2
LBCTL
LALE
LGPL2/LOE/LFRE
LWE0_N
UART_SOUT1
READY_P1
LA27
LA16
LGPL3/LFW
PLGPL5
76
P2020 Strapping Options
Reset
Configuration
Name
cfg_sys_pii[0:2]
cfg_ddr_pii[0:2]
cfg_core0pii[0:2]
cfg_core1pii[0:2]
cfg_cup0_boot
cfg_cpu1_boot
cfg_boot_seq[0:1]
Config
Default
Resistor Description
Value
Options
4:1 ratio CCB clock:
Yes 000
SYSCLK = 100MHz, CCB=400Mhz
8:1 ratio, DDRCLK=100MHz,
Yes 011
DDRPLL (data rate) = 800MHz
ENP1:
3:1 ratio, CCB clock= 400MHz,
Core clock=1200MHz
Yes 110
101
ENP2:
2.5:1 ratio, CCB clock= 400MHz,
Core clock=1000MHz
ENP1:
110
3:1 ratio, CCB clock= 400MHz,
Core clock=1200MHz
Yes
ENP2:
101
2.5:1 ratio, CCB clock= 400MHz,
Core clock=1000MHz
CPU0 boot without waiting.
Yes 10
CPU1 holdoff
Boot sequencer is disabled.
Yes 11
No I2C ROM is accessed (default)
MVME2502 Installation and Use (6806800R96G)
Functional Description