Pld Sequence Register; Pld Power Good Monitor Register; Table 5-8 Pld Sequence Register; Table 5-9 Pld Power Good Monitor Register - SMART Embedded Computing Penguin Edge MVME250 Series Installation And User Manual

Memory Maps and Registers
5.5.5

PLD Sequence Register

The MVME2502 PLD provides an 8-bit register which contains the sequence of the PLD
which is in synchrony with the PCB version.
Table 5-8
REG
Bit
Bit
Field
OPER
RESET
5.5.6

PLD Power Good Monitor Register

The MVME2502 PLD provides an 8-bit register which indicates the instantaneous status of
the supply's power good signals.
Table 5-9
REG
Bit
Field
OPER
RESET 0
Field Description
PWR_V1P05_PWRGD
PWR_V1P2_PWRGD
PWR_V1P8_PWRGD
PWR_V3P3_PWRGD
PWR_V2P5_PWRGD
102
PLD Sequence Register
PLD Revision Register - 0xFFDF0007
7 6
7 6
PLD_REV
R
0x00
PLD Power Good Monitor Register
PLD PWRDG_MNTR - 0xFFDF0012
7 6 5
PWR_V1 PWR_V1
RSVD P05_PW P2_PWR
RGD GD
R
0 0
1.05V Core supply power good indicator
1.2V Supply power good indicator
1.8V Supply power good indicator
3.3V Supply power good indicator
2.5V Supply power good indicator
5 4 3
5 4 3
4 3
PWR_V1 PWR_V3
P8_PWR P3_PWR
GD GD
0 0
MVME2502 Installation and Use (6806800R96L)
Memory Maps and Registers
2 1 0
2 1 0
2 1 0
PWR_V2 PWR_V1 PWR_V1
P5_PWR P2_SW_ P5_PWR
GD PWRGD GD
0 0 0