Clock Distribution - SMART Embedded Computing MVME2502 Installation And Use Manual

EHTR
EAD
7.7

Clock Distribution

The clock function generates and distributes all the clocks required for system operation.
The ICS9FG108 is used to generate all the required PCI-E clocks. The 25MHz clocks for
the Ethernet PHY and SATA bridge are supplied by ICS83905 device. Most of the QorIQ
P2020 clocks are generated by ICS840S07I device. Additional clocks required by individual
devices are generated near the devices using individual oscillators. The following table lists
the clocks required on the MVME2502 along with the frequency and source.
Table 7-6
Device
QorIQ P2020
QorIQ P2020
QorIQ P2020
QorIQ P2020
ICS840S07I
88SE9125
ICS9FG108
BCM54616S
BCM54616S
BCM54616S
XMC
QorIQ P2020
TSI384
TSI384
MVME2502 Installation and Use (6806800R96G)
Extended hold time on read accesses.
0 - The memory controller generates normal timing. No additional cycles are
inserted
External address latch delay
0 - No additional bus clock cycles (LALE asserted for one bus clock cycle
only)
Clock Distribution
Clock Signal
CPU_SYSCLK
CPU_DDR_CLK
CLK_PCI_BR3
EC_GTX_CLK125
CLK_25MHZ_ICS840S07
CLK_88SE9125_25MHZ
CLK_25MHZ_ICS9FG108
BP_PHY_25MHZ_CLK
FP_PHY_25MHZ_CLK
SW_25MHZ_CLK
CLK_XMC1
SD_REF_CLK
CLK_PCIEC1
CLK_PCIEC3
Programming Model
Clock Tree
Frequency
Source
100MHz ICS840S07I
100MHz ICS840S07I
133MHz ICS840S07I
125MHz ICS840S07I
25MHz ICS83905AGILF
25MHz ICS83905AGILF
25MHz ICS83905AGILF
25MHz ICS83905AGILF
25MHz ICS83905AGILF
25MHz ICS83905AGILF
100MHz ICS9FG108
100MHz ICS9FG109
100MHz ICS9FG110
100MHz ICS9FG111
VIO
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
DIFF
DIFF
DIFF
DIFF
133