Table of Contents
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Memory Maps and Registers
Table 5-3
Device Memory Range
msi CCSR
mpic CCSR
Global Utilities CCSR
L2 Cache Mem
5.5
Programmable Logic Device (PLD) Registers
5.5.1
PLD Revision Register
The MVME2502 provides a PLD revision register that is read by the system software to
determine the current version of the timers/registers PLD.
Table 5-4
REG
Bit
Field
OPER
RESET
Field Description
PLD_REV
5.5.2
PLD Year Register
The MVME2502 PLD provides an 8-bit register which contains the build year of the
timers/registers PLD.
Table 5-5
REG
Bit
100
Linux Devices Memory Map (continued)
PLD Revision Register
PLD Revision Register - 0xFFDF0000
7
6
5
PLD_REV
R
0x01
8-bit field containing the current timer/register PLD revision. The
revision number starts at 01.
PLD Year Register
PLD Year Register - 0xFFDF0004
7
6
5
Memory Area
0xffe41600 0xffe4167f
0xffe40000 0xffe7ffff
0xffee0000 0xffee0fff
0xf0f80000 0xf0ffffff
4
3
2
4
3
2
MVME2502 Installation and Use (6806800R96L)
Memory Maps and Registers
Size
128B
256KB
4KB
512KB
1
0
1
0
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