Emmc Reset Register - SMART Embedded Computing MVME2502 Installation And Use Manual

Memory Maps and Registers
Clear_Cause
CPU_RESET
WD_TIMEOUT
LRSTO
Sft_RST
5.5.17

EMMC Reset Register

The MVME2502 provides a register for EMMC Reset.
Table 5-20
REG EMMC Reset Register
Bit 7
Field RSVD
OPER R
RESET 0
Field Description
EMMC_RST_N
108
Clear Reset Reason (self clearing)
1 - Clear Reason
0 - None
CPU_HRESET_REQ_L Reset Reason
1 - Reset is due to CPU_HRESET_REQ_L signal
0 -None
Watchdog Timeout Reset Reason
1 - Reset is due to watchdog timing out
0 - None
TSI LRSTO Reset Reason
1 - Reset is due to LRSTO signal
0 - None
Soft Reset - Reset Reason
1 - Reset is due to Soft_RST register being set, or the front
panel switch being pressed more than three
0 - None
PLD Shutdown and Reset Control and Reset Reason Register
6 5
RSVD RSVD
0 0
EMMC Reset Bit
1 - Reset is deasserted
0 - Reset is asserted (write 0 to reset EMMC)
4 3 2
RSVD RSVD RSVD
0 X X
MVME2502 Installation and Use (6806800R96G)
Memory Maps and Registers
1 0
EMMC_R
RSVD
ST_N
R/W
X X