Programming Model; Overview; Reset Configuration - SMART Embedded Computing MVME2502 Installation And Use Manual

Programming Model

7.1

Overview

This chapter includes additional programming information for the MVME2502.
7.2

Reset Configuration

The MVME2502 supports the power-on reset (POR) pin sampling method for processor
reset configuration. Each option and the corresponding default setting are described in the
following table.
Table 7-1
CONFIG
1 CCB Config
DDR PLL
2
Config
3 Core 0 PLL
4 Core 1 PLL
CPU Boot
5
Config
MVME2502 Installation and Use (6806800R96G)
POR Configuration Settings
CONFIG PINS
LA[29:31]
TSEC_1588_CLK_
OUT
TSEC_1588_PULSE
_OUT1
TSEC_1588_PULSE
_OUT2
LBCTL, LALE
LGPL2/LOE/LFRE
LWE0,
UART_SOUT1
LA27, LA16
CONFIG SELECTION
41: CCB CLOCK-
000
400MHz
001 8:1 DDR PLL-800MHz
3:1 CORE CLOCK PLL
110
(1200MHz)
2:1 CORE CLOCK PLL
100
(800MHz)
3:1 CORE CLOCK PLL
110
(1200MHz)
2:1 CORE CLOCK PLL
100
(800MHz)
e500 core 0 is allowed
to boot without waiting
for configuration by an
external master, while
10 e500 core 1 is
prevented from booting
until configured by an
external master or the
other core.
Chapter 7
REMARKS
DDR rate is twice the
value of the DDR
controller frequency,
which is then divided
by two through the
software.
For 1200MHz board
configuration
For 800MHz board
configuration
For 1200MHz board
configuration
For 800MHz board
configuration
125