Table of Contents
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Table 4-1
GPIO bit CPU Pin #
10
09
08
07
06
05
04
03
02
01
00
4.2.12
Security Engine (SEC) 3.1
The integrated security engine of the P2020 is designed to off load intensive security
functions like key generation and exchange, authentication and bulk encryption from the
processor core. It includes eight different execution units where data flows in and out of an
EU.
NOTE: The standard versions of the MVME2502 do not use the encryption enabled
versions of the P2020 processor.
MVME2502 Installation and Use (6806800R96G)
P2020 GPIO Functions (continued)
Function
A25
Not connected
A24
Not connected
F22
Not connected
R25
Not connected
R29
Connected to pin T6 of the CPLD (unused input)
R24
Connected to pin R6 of the CPLD (unused input)
Connected to INTA of the QUART. Programmed as a discrete input or
U29
to generate IRQ11.
Also connected to pin P16 of the CPLD. (unused input)
N24
Connected to pin P15of the CPLD
Connected to Pin R16 of the CPLD. Programmed to generate a IRQ09
interrupt to the CPU based on contents of the CPLD GPIO2 interrupt
P29
register. For more information see
page 106
Connected to INTA_N of the DS1337 Real Time Clock (RTC).
R26
Programmed as a discrete input or to generate IRQ08
Connected to LED_P21[2] of the BCM5482S. Programmed as a
R28
discrete input or to generate IRQ07.
PLD GPIO2 Interrupt Register on
.
Functional Description
75
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