Sun Oracle Sun Server X4-2 Service Manual page 82

Each processor has four channels and can support two DIMMs per channel for a
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maximum of eight quad-rank (QR) Load Reduced DIMMs (LRDIMMs), dual-rank
(DR) DIMMs, or single-rank (SR) DIMMs.
The server supports 32-GB QR LRDIMMs in addition to 8-GB and 16-GB
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Registered DIMMs (RDIMMs).
You cannot mix LRDIMMs and RDIMMs in the same server. If you choose to
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install 32-GB QR LRDIMMs in the server, you cannot install any 8-GB or 16-GB
single-rank or dual-rank RDIMMs.
If a you are installing a mix of RDIMM sizes (for example, 8-GB and 16-GB), install
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the larger RDIMMs first, then the smaller RDIMMs, until all of the RDIMMs are
installed.
If you are installing QR LRDIMMs within a channel, populate the blue sockets
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prior to populating the white sockets.
Note – While the processor used in the server supports four modes of
operation—Independent Channel Mode, Lockstep Channel Mode, Mirrored Channel
Mode, and, Device Tagging Mode—the server supports the Independent Channel
Mode only.
Note – Each processor (P0, P1) has eight associated DIMM sockets, numbered D0,
D1, D2, D3, D4, D5, D6, and D7.
DIMMs should be installed into DIMM sockets starting with P0 D0 and
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alternating between sockets associate with P0 and matching sockets for P1, first
filling the blue sockets and then the white. For an example of a configuration that
follows this rule, see
Performance" on page
For maximum performance, apply the following rules:
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All memory installed in the system will operate at the same speed. DIMM
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operational speed, or frequency, is limited to the lowest speed determined by each
of the following factors:
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68 Sun Server X4-2 Service Manual • May 2014
"DIMM Population Example for Optimal System
65.
The best performance is ensured by preserving symmetry. For example, add
four of the same kind of DIMMs, one per memory channel, and if the server has
two processors, ensure that both processors have the same size of DIMMs
installed in the same manner.
For optimal performance, the memory installation should be identical across
both sockets. Populate each socket with QR, DR, or SR DIMMs in sets of four,
one per memory channel.
Maximum memory frequency supported by processor
Maximum memory frequency supported by the installed DIMMs
Memory configuration within a channel