Mc68Vz328 To S1D13706 Interface; Hardware Description - Epson S1D13706 Technical Manual

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4 MC68VZ328 to S1D13706 Interface

When connecting the S1D13706 RESET# pin, the system designer should be aware of all

conditions that may reset the S1D13706 (e.g. CPU reset can be asserted during wake-up

from power-down modes, or during debug states).

Figure 4-1: Typical Implementation of MC68VZ328 to S1D13706 Interface

Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor

Issue Date: 01/02/26

The interface between the S1D13706 and the MC68VZ328 does not requires any external

glue logic. Chip select module B is used to provide the S1D13706 with a chip select and

A17 is used to select between memory and register accesses.

In this example, the DTACK signal is made available for the S1D13706. Alternately, the

S1D13706 can guarantee a maximum cycle length that the Dragonball VZ handles by

inserting software wait states (see Section 4.2.2, "MC68VZ328 Chip Select and Pin

Configuration" on page 13). A single resistor is used to speed up the rise time of the WAIT#

(DTACK) signal when terminating the bus cycle.

The following diagram shows a typical implementation of the MC68VZ328 to S1D13706

using the Dragonball host bus interface. For further information on the Dragonball Host

Bus interface and AC Timing, refer to the S1D13706 Hardware Functional Specification,

document number X31B-A-001-xx.

System RESET

X31B-G-016-02

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