Table 6-8: Hitachi Sh-3 Interface Timing - Epson S1D13706 Technical Manual

Epson Research and Development
Vancouver Design Center
Symbol
f
Bus Clock frequency
CKIO
T
Bus Clock period
CKIO
t1
Bus Clock pulse width low
t2
Bus Clock pulse width high
t3
A[16:1], M/R#, RD/WR# setup to CKIO
t4
CSn# high setup to CKIO
t5
BS# setup
t6
BS# hold
t7
CSn# setup
t8
A[16:1], M/R#, RD/WR# hold from CS#
t9a
RD# or WEn# asserted for MCLK = BCLK (max. MCLK = 50MHz)
RD# or WEn# asserted for MCLK = BCLK ÷ 2
t9b
RD# or WEn# asserted for MCLK = BCLK ÷ 3
t9c
RD# or WEn# asserted for MCLK = BCLK ÷ 4
t9d
t10
Falling edge RD# to D[15:0] driven (read cycle)
t11
Rising edge CSn# to WAIT# high impedance
t12
Falling edge CSn# to WAIT# driven low
t13
CKIO to WAIT# delay
t14
D[15:0] setup to 2
t15
D[15:0] hold (write cycle)
t16
WAIT# rising edge to D[15:0] valid (read cycle)
t17
Rising edge RD# to D[15:0] high impedance (read cycle)
1. t14 is the delay from when data is placed on the bus until the data is latched into the write buffer.
Note
Hardware Functional Specification
Issue Date: 01/11/13

Table 6-8: Hitachi SH-3 Interface Timing

Parameter
nd
CKIO after BS# (write cycle) (see note 1)
Minimum one software WAIT state is required.
2.0V 3.3V
Min Max Min
20
1/f 1/f
CKIO CKIO
22.5 6.8
22.5 6.8
0 1
0 1
3 1
7 2
0 1
0 0
8.5
11.5
13.5
18.5
5 24 3
4 24 2
3 24 2
6 45 4
1 0
0 0
0
5 31 3
Page 43
Unit
Max
66 MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
8.5 T
CKIO
11.5 T
CKIO
13.5 T
CKIO
18.5 T
CKIO
12 ns
10 ns
12 ns
18 ns
ns
ns
2 ns
12 ns
S1D13706
X31B-A-001-08