Figure 6-27: Generic Tft Panel Timing - Epson S1D13706 Technical Manual

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6.4.8 Generic TFT Panel Timing
VPS
FPFRAME
FPLINE
DRDY
FPDAT[17:0]
HPS
FPLINE
FPSHIFT
DRDY
FPDAT[17:0]
VT = Vertical Total
VPS = FPFRAME Pulse Start Position
VPW = FPFRAME Pulse Width
VDPS = Vertical Display Period Start Position
VDP = Vertical Display Period
HT = Horizontal Total
HPS = FPLINE Pulse Start Position
HPW = FPLINE Pulse Width
HDPS = Horizontal Display Period Start Position = [(REG[17h] bits 1-0, REG[16h] bits 7-0) + 5] pixels
HDP = Horizontal Display Period
*For TFT panels, the HDP must be a minimum of 8 pixels and must be increased by multiples of 8.
*Panel Type Bits (REG[10h] bits 1-0) = 01 (TFT)
*FPLINE Pulse Polarity Bit (REG[24h] bit 7) = 0 (active low)
*FPFRAME Polarity Bit (REG[20h] bit 7) = 0 (active low)
S1D13706
X31B-A-001-08
VPW
VDPS
HPW
HDPS
invalid

Figure 6-27: Generic TFT Panel Timing

= [(REG[19h] bits 1-0, REG[18h] bits 7-0) + 1] lines
= (REG[27h] bits 1-0, REG[26h] bits 7-0) lines
= [(REG[24h] bits 2-0) + 1] lines
= (REG[1Fh] bits 1-0, REG[1Eh] bits 7-0) lines
= [(REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) + 1] lines
= [((REG[12h] bits 6-0) + 1) x 8] pixels
= [(REG[23h] bits 1-0, REG[22h] bits 7-0) + 1] pixels
= [(REG[20h] bits 6-0) + 1] pixels
= [((REG[14h] bits 6-0) + 1) x 8] pixels
VT (= 1 Frame)
VDP
HT (= 1 Line)
HDP
Epson Research and Development
Vancouver Design Center
invalid
Hardware Functional Specification
Issue Date: 01/11/13