Table 6-7: Hitachi Sh-4 Interface Timing - Epson S1D13706 Technical Manual

Epson Research and Development
Vancouver Design Center
Symbol
f
Clock frequency
CKIO
T
Clock period
CKIO
t1
Clock pulse width low
t2
Clock pulse width high
t3
A[16:1], M/R#, RD/WR# setup to CKIO
t4
A[16:1], M/R#, RD/WR# hold from CSn#
t5
BS# setup
t6
BS# hold
t7
CSn# setup
t8
CSn# high setup to CKIO
t9a
RD# or WEn# asserted for MCLK = BCLK (max. MCLK = 50MHz)
RD# or WEn# asserted for MCLK = BCLK ÷ 2
t9b
RD# or WEn# asserted for MCLK = BCLK ÷ 3
t9c
RD# or WEn# asserted for MCLK = BCLK ÷ 4
t9d
t10
Falling edge RD# to D[15:0] driven (read cycle)
t11
Falling edge CSn# to RDY# driven high
t12
CKIO to RDY# low
t13
CSn# high to RDY# high
t14
Falling edge CKIO to RDY# high impedance
t15
D[15:0] setup to 2
t16
D[15:0] hold (write cycle)
t17
RDY# falling edge to D[15:0] valid (read cycle)
t18
Rising edge RD# to D[15:0] high impedance (read cycle)
1. t15 is the delay from when data is placed on the bus until the data is latched into the write buffer.
Note
Hardware Functional Specification
Issue Date: 01/11/13

Table 6-7: Hitachi SH-4 Interface Timing

Parameter
nd
CKIO after BS# (write cycle) (see note 1)
Minimum one software WAIT state is required.
2.0V 3.3V
Min Max Min
20
1/f 1/f
CKIO CKIO
22.5 6.8
22.5 6.8
0 1
0 0
3 1
7 2
0 1
0 2
8.5
11.5
13.5
18.5
5 24 3
3 19 3
5 42 4
5 35 4
5 38 4
1 0
0 0
0
5 31 3
Page 41
Unit
Max
66 MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
8.5 T
CKIO
11.5 T
CKIO
13.5 T
CKIO
18.5 T
CKIO
12 ns
12 ns
18 ns
14 ns
14 ns
ns
ns
2 ns
12 ns
S1D13706
X31B-A-001-08