Host Bus Interface Signals - Epson S1D13706 Technical Manual

Epson Research and Development
Vancouver Design Center

3.2 Host Bus Interface Signals

Interfacing to the Toshiba MIPS TMPR3905/3912 Microprocessors
Issue Date: 01/02/23
The Host Bus Interface requires the following signals.
• CLKI is a clock input required by the S1D13706 Host Bus Interface as a source for its
internal bus and memory clocks. This clock is typically driven by the host CPU system
clock. For example, DCLKOUT from the Toshiba TMPR3905/12.
• The address inputs AB[12:0] are connected directly to the TMPR3905/12 address bus.
Since the TMPR3905/12 has a multiplexed address bus, the other address inputs
A[16:13] must be generated using an external latch controlled by the address latch
enable signal (ALE). The low data byte on the TMPR3905/12 data bus for 16-bit ports is
D[31:24] and connects to the S1D13706 low data byte, D[7:0]. The high data byte on
the TMPR3905/12 data bus for 16-bit ports is D[23:16] and connects to the S1D13706
high data byte, D[15:0]. The hardware engineer must ensure that CNF4 selects the
proper endian mode upon reset.
• Chip Select (CS#) is driven by external decoding circuitry to select the S1D13706.
• M/R# (memory/register) selects between memory or register accesses. This signal may
be connected to an address line, allowing system address A17 to be connected to the
M/R# line. This address line must be generated from the external latch used to provide
the upper addresses to the S1D13706.
• WE1# is connected to CARD1CSH* and is the high byte enable for both read and write
cycles.
• WE0# is connected to CARDIOWR* (the write enable signal) and must be driven low
when the Toshiba TMPR3905/12 is writing data to the S1D13706.
• RD# is connected to CARDIORD* (the read enable signal) and must be driven low
when the Toshiba TMPR3905/12 is reading data from the S1D13706.
• WAIT# connects to CARD1WAIT* and is a signal which is output from the S1D13706
to the TMPR3905/12 that indicates when data is ready (read cycle) or accepted (write
cycle) on the host bus. Since host CPU accesses to the S1D13706 may occur asynchro-
nously to the display update, it is possible that contention may occur in accessing the
S1D13706 internal registers and/or display buffer. The WAIT# line resolves these
contentions by forcing the host to wait until the resource arbitration is complete.
• The Bus Status (BS#) and Read/Write (RD/WR#) signals are not used in this implemen-
tation of the Toshiba TMPR3905/12 using the Generic #2 Host Bus Interface. These
pins must be tied high (connected to HIO V ).
DD
Page 11
S1D13706
X31B-G-002-02