Vr4181A To S1D13706 Interface; Hardware Description - Epson S1D13706 Technical Manual

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4 VR4181A to S1D13706 Interface

When connecting the S1D13706 RESET# pin, the system designer should be aware of all

conditions that may reset the S1D13706 (e.g. CPU reset can be asserted during wake-up

from power-down modes, or during debug states).

Figure 4-1: Typical Implementation of VR4181A to S1D13706 Interface

X31B-G-008-02

The NEC VR4181A microprocessor is specifically designed to support an external LCD

controller by providing the internal address decoding and control signals necessary. By

using the Generic # 2 Host Bus Interface, no glue logic is required to interface the

S1D13706 to the NEC VR4181A.

A pull-up resistor is attached to WAIT# to speed up its rise time when terminating a cycle.

#MEMCS16 of the NEC VR4181A is connected to #LCDCS to signal that the S1D13706

is capable of 16-bit transfers.

BS# (bus start) and RD/WR# are not used by the Generic #2 Host Bus Interface and should

be tied high (connected to HIO V

The diagram below shows a typical implementation of the VR4181A to S1D13706

System RESET

Interfacing to the NEC VR4181A™ Microprocessor

Epson Research and Development

Vancouver Design Center

Issue Date: 01/02/23

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