Epson S1D13706 Technical Manual page 662

Page 10 Epson Research and Development
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Figure 2-2: illustrates a typical variable-latency IO access write cycle on the SA-1110 bus.
A[25:0]
ADDRESS VALID
nCS4
nWE
nOE
RDY
D[31:0]
DATA VALID
nCAS[3:0]
Figure 2-2: SA-1110 Variable-Latency IO Write Cycle
S1D13706 Interfacing to the Intel StrongARM SA-1110 Microprocessor
X31B-G-019-02 Issue Date: 02/06/26